Re: Oops (Concertina II Going Around in Circles)

John Savard <quadibloc@servername.invalid> schrieb:

On Fri, 10 May 2024 17:27:10 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:
>

Or skip to the end and only invent AVX while skipping the soon-to-be
redundant intermediate stages.

>
Well, I went to 256-bit short vectors as a permanent part of the
architecture, with long vectors as the next step.
>
But what about crypto assist instructions, as another example?

You will probably want to look at AES for this.  AES operates on
16-byte blocks, so having 128-bit registers is natural.

AES256 also needs 15 separate keys, which should be kept in
registers if you are doing things on a CPU, so because you
also need intermedite results and also to load/store data,
so 32 128-bit registers would be a good fit.  Look at POWER's
vcipher and vcipherlast as an example.

These register would also be a good fit for 128-bit IEEE floating
point, which only POWER at the moment supports in hardware, plus
those SIMD things that do not come in loops (aka SLP).