Re: Making Lemonade (Floating-point format changes)

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Sujet : Re: Making Lemonade (Floating-point format changes)
De : cr88192 (at) *nospam* gmail.com (BGB)
Groupes : comp.arch
Date : 20. May 2024, 01:40:27
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <v2e2ld$3k7lr$1@dont-email.me>
References : 1 2 3 4 5 6 7 8 9 10 11 12
User-Agent : Mozilla Thunderbird
On 5/19/2024 4:16 PM, MitchAlsup1 wrote:
BGB wrote:
 
On 5/19/2024 11:37 AM, Terje Mathisen wrote:
Thomas Koenig wrote:
So, I did some more measurements on the POWER9 machine, and it came
to around 18 cycles per FMA.  Compared to the 13 cycles for the
FMA instruction, this actually sounds reasonable.
>
The big problem appears to be that, in this particular
implementation, multiplication is not pipelined, but done by
piecewise by addition.  This can be explained by the fact that
this is mostly a decimal unit, with the 128-bit QP just added as
an afterthought, and decimal multiplication does not happen all
that often.
>
A fully pipelined FMA unit capable of 128-bit arithmetic would be
an entirely different beast, I would expect a throughput of 1 per
cycle and a latency of (maybe) one cycle more than 64-bit FMA.
>
The FMA normalizer has to handle a maximally bad cancellation, so it needs to be around 350 bits wide. Mitch knows of course but I'm guessing
>
that this could at least be close to needing an extra cycle on its own and/or heroic hardware?
>
 
This sort of thing is part of what makes proper FMA hopelessly expensive.
 Getting the LoB correctly rounded showed up the generation prior to
FMAC showing up.
 
Well, in this case, I have neither in a proper sense.
FMAC operators were sorta faked, but mostly exist because they were needed for RV64G, but double-rounded (and not able to expose anything that exists below the ULP, unlike proper FMA).

            Granted, full FMA also allows faking higher precision using
>
SIMD vector operations, with math that does not work with double-rounded
>
FMA instructions.
 It also enabled error free floating point calculations, but no existing
FP implementation allows exact FP calculations that do not ALSO SET the
inexact flag !?!? {Whereas My 66000 gets this right}
 
Dunno.
It seems like the existence of anything below the ULP justifies setting the inexact flag...

Well, and also an issue if one can "just barely" afford to have a single
>
double-precision unit.
 This is NOT an architectural issue, but an implementation choice issue.
 
Absent things like microcode or traps, architectural and implementation choices are closely tied together. Can't have instructions for things which one can't afford the hardware cost to implement.
Well, and the usefulness of an FPU is dependent on  performance. Inaccurate FPU can still be useful, but slow FPU is not.

Though, the trick of possibly having four 27-bit multiplies which combine into a virtual 54 bit multiplier seems like an interesting possibility, though not great as DSP's don't natively handle this size (and would be too expensive to stretch it out with LUTs). Likely, one would need to build it from 34*34->68 bit multipliers (each costing 4
DSPs).
 This is your implementation choice coloring what you take as
architectural
decisions.
 
In terms of DSP cost, it would be higher than the current solution:
   16 vs 6+4 (10).
But, possibly lower LUT cost (in both the Binary32 and Binary64 multipliers, the shortfall is made up using smaller LUT-based
multipliers).
 We can now fit (5nm) hundreds of GBOoO cores on a single die. The
difference between a 53×53 tree and a 64×64 tree (makes all problems vanish) is
not
visible at this level (100+ cores on a die).
 This is your implementation choice coloring you thoughts.
 
I can afford FPGAs...
I can't afford to get an ASIC made.
So, implementation choices here are:
   FPGA;
   Nothing.
Could at least theoretically do printable semiconductors, but as-is, it is likely to be significantly lower density and speed than an FPGA. Not so much density limited by DPI, but more page alignment.
Would likely need a different type of printer (from something like a normal inkjet) for repeatable alignment, likely something that holds the sheet in a rigid frame and moves the print-head CNC style; probably with a heater built into the sheet frame.
One big uncertainty is the valves, would need to figure out a way to make valves that can quickly deliver a small but controlled amounts of ink. One idea could be to make a small check-valve into a cylinder, with something like a sowing needle being used as a piston (driven by a small solenoid).
Would need to drill some absurdly small holes though.
Well, or could drill some moderately small holes, and then make the hole smaller by covering it with a plastic lamination, and poking a hole with a sewing pin or similar (say, drill bits much under around 0.040" or so aren't really a thing).
Though, theoretically, #80 drills exist, or 0.0135"... Would ideally want some way to make a hole that is ~ 0.002", and some way to accurately move a pin less than 0.005", but...
Well, or maybe figure out how to salvage the needed parts from (or repurpose) some old inkjet cartridges.

Though, with the combiner option, one could make a case for, say, a:
   S.E15.F66.Z46 format (Z=zeroed/ignored).
 
Well, and/or accept the wonk of a Binary128 which produces 112 bits of mantissa, but only uses the high 66 bits or so, but generally this was worse for some things in some tests than one which simply zeroes the low-order bits.
 But it allows for exact FP arithmetic, and for FMAC, ..... and lots of other good properties.
 What kind of car do you drive ??
 
I don't drive a car...
I tend to fairly rapidly get tired out if trying to drive.

But, OTOH, 66*66->112 would allow for possible trickery to fake a full Binary128 FMUL in software as a multi-part process (when combined with a
>
Binary128 FADD).
 A 1-bit wide machine can perform 128 × 128 + 128 FMACs -- it just takes
more time.
 
I had before considered possibly allowing Binary128 FMUL via a Shift-Add unit, but it would also be slower than doing it in software.

....
 
Terje
>

Date Sujet#  Auteur
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