Re: Byte Addressability And Beyond

John Levine wrote:

According to Terje Mathisen  <terje.mathisen@tmsw.no>:

It's almost like the perfect application of risc instruction design:
a long sequence of individual instructions of conditional branches,
bit field extracts, inserts, and shifts, is replace in HW by
a small number of muxes that can to the same in one clock.

>
If that CU14 can also return the number of bytes consumed, along with
the resulting 32-bit character, then it would be perfect. Is that what
it is doing?

 You give it registers with two addresses and two lengths, and it
converts the source UTF-8 code points to destination UTF-32 until it
runs out of input, fills the output, gets an invalid character, or an
interrupt. It updates the addresses and lengths. Other than optionally
checking for invalid UTF-8 it does not interpret the code points.
 The condition code tells you which it was.  If it was an interrupt, you just
branch back and keep going.
 There's an extra cost flag whether to test for invalid UTF-8.
 Read all about it: https://www.vm.ibm.com/library/other/22783213.pdf
 It's on page 7-251.
 

Thanks!
I did read all of it, and it was pretty close to how I would have designed a sw function to do the same, except for the very funky ABI:
Both source and destination _must_ be an even register number, with the following odd register providing the count/length.
Just from this little snippet I'm pretty sure this instruction has a sizeable startup overhead, compiler support is probably in the form of an intrinsic that knows about the need to allocate two pairs of register, each pair starting at an even-numbered register.
Terje
--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"