Re: My 66000 and High word facility

MitchAlsup1 <mitchalsup@aol.com> wrote:

On Sun, 11 Aug 2024 0:46:09 +0000, Brett wrote:
 

MitchAlsup1 <mitchalsup@aol.com> wrote:

<snip>

 
High registers is mostly marketing vapor ware extension for you, see if
anyone cares and put them on a list for when a market for that extension
pops up.
 
The lack of CPU’s with 64 registers is what makes for a market, that 4%
that could benefit have no options to pick from. You would be happy to
have control of a market that big. Point customers at a compiler
configured
for 64 registers and say that with high registers and inline constants
that
is what they could expect for code generation.

 
I agree with the lead in, and disagree with where you took it.
 
Let up postulate that having 64 registers is a 10% win (overstating
the size of its win my 2.5×) but that 98% of subroutines don't need
64-registers. So, 98% gains nothing and 2% gains 10%
 
    0.98*1.0 + 0.02*1.1 = 1.002
or
0.2% gain.

I agree with this, but you have 4% of the market where more registers gives
a much larger speedup. You would be glad to have that much market share.

If there is demand for high registers you will probably just spin a CPU
arch with more registers, but that will never happen if you never ask.

 
The thing is that one you go down the GBOoO route, your lack of
registers
"namable in ASM" ceases to become a performance degrader. With renaming
one can have R7 in use 40 times in a 100 instruction deep execution
window.

If this was true we would have 16 or even 8 visible registers, and all
would be fine. x86 does mostly fine with 16, of course x84 had fab and
cubic dollar advantages that dwarfed the register limit.

This
is the definition of vapor ware, a free market survey. You can even add
more registers as an incompatible extension, if fact you should.

 
I will leave stuff like this to you.

I do agree that high registers to double your register count is far cleaner
for the instruction set than going to 64 separate registers. You have much
of high register implemented anyway if you support integer vector
operations in the integer register file like MIPS, or have a unified
register file, be it visible or not.

64 separate registers was a bridge to far, but it was an interesting
exercise before it crashed and burned due to the bits being not quite
available.
So close, yet so far. I could not make it work.