Re: Tonights Tradeoff

On 2024-09-07 10:41 a.m., MitchAlsup1 wrote:

On Sat, 7 Sep 2024 2:27:40 +0000, Robert Finch wrote:
 

Making the scalar register file a subset of the vector register file.
And renaming only vector elements.
>
There are eight elements in a vector register and each element is
128-bits wide. (Corresponding to the size of a GPR). Vector register
file elements are subject to register renaming to allow the full power
of the OoO machine to be used to process vectors. The issue is that with
both the vector and scalar registers present for renaming there are a
lot of registers to rename. It is desirable to keep the number of
renamed registers (including vector elements) <= 256 total. So, the 64
scalar registers are aliased with the first eight vector registers.
Leaving only 24 truly available vector registers. Hm. There are 1024
physical registers, so maybe going up to about 300 renamable register
would not hurt.

 Why do you think a vector register file is the way to go ??

I think vector use is somewhat dubious, but they have some uses. In many cases data can be processed just fine without vector registers. In the current project vector instructions use the scalar functional units to compute, making them no faster than scalar calcs. But vectors have a lot of code density where parallel computation on multiple data items using a single instruction is desirable. I do not know why people use vector registers in general, but they are present in some modern architectures. Qupls vector registers are 512 bits wide (8 64-bit elements). Bigfoot’s vector registers are 1024 bits wide (8 128-bit elements).
One use I am considering is the graphics transform function for doing rotates and translates of pixels. It uses a 3x4 matrix. ATM this is done with specially dedicated registers, but the matrix could be fit into a vector register and the transform function applied with it. Another use is neural net instructions.
I added a fixed length vector type to the compiler to make it easier to experiment with vectors.
The processor handles vector instructions by replicating them one to eight times depending on the vector length. It then fixes up the register spec fields with incrementing register numbers for each instruction. They get fed into the remainder of the CPU as a series of scalar instructions.