Re: arm ldxr/stxr vs cas

On 9/7/2024 5:59 PM, MitchAlsup1 wrote:

On Sat, 7 Sep 2024 23:16:35 +0000, Chris M. Thomasson wrote:
 

On 9/7/2024 4:14 PM, Chris M. Thomasson wrote:
[...]

When I am using CAS I don't really expect it to fail willy nilly even if
the comparands are still the same. Weak vs Strong. Still irks me a bit.
;^)

>
There are algorithms out there, usually state machines that depend on
strong cas. When a CAS fails, it depends on it failing because the
comparands were actually different...

 Leading to ABA failures::
 Do you really want the following CAS to succeed ??
      LD    R19,[someMemoryValue]
..
interrupt delays program execution for 1 week
..
     CAS   R17,R19,[someMemoryLocation]
 Given that the someMemoryLocation is accessible to other programs
while tis one is sleeping ??
 Thus, it seems reasonable to fail a CAS when one cannot determine
if the memory location has been changed and changed back in the
mean time.

I think Scott Lurndal mentioned something about CAS or something on windows that will assert the bus lock after a lot of failures...