Re: Tonights Tradeoff - Background Execution Buffers

Today I am wondering how many predicate registers are enough. Scanning webpages reveals a variety. The Itanium has 64-predicates, but they are used for modulo loops and rotated. Rotating register is Itaniums method of register renaming, so it needs more visible registers. In a classic superscalar design with a RAT where registers are renamed, it seems like 64 would be far too many. Cray had eight vector mask registers. I think the RISCV- Hwatcha has 16 if I looked at the diagram correctly.
I cannot see the compiler making use of very many predicate registers simultaneously. Since they are not used simultaneously, and register renaming is in effect, there should not be a great need for predicate registers.
Suppose one wants predicated logic in a loop with the predicate being set outside of the loop. It may be desirable to have several blocks of logic predicated by different predicates in the loop. It is likely desirable to have more than one predicate then.
->Reserved four bits in the instruction for predicates. Do not want to waste bits though. Using a 64-bit instruction.