Sujet : Re: 80286 protected mode
De : terje.mathisen (at) *nospam* tmsw.no (Terje Mathisen)
Groupes : comp.archDate : 14. Oct 2024, 15:40:26
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vejagr$181vo$1@dont-email.me>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13 14
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David Brown wrote:
On 13/10/2024 21:21, Terje Mathisen wrote:
David Brown wrote:
On 10/10/2024 20:38, MitchAlsup1 wrote:
On Thu, 10 Oct 2024 6:31:52 +0000, David Brown wrote:
>
On 09/10/2024 23:37, MitchAlsup1 wrote:
On Wed, 9 Oct 2024 20:22:16 +0000, David Brown wrote:
>
On 09/10/2024 20:10, Thomas Koenig wrote:
David Brown <david.brown@hesbynett.no> schrieb:
>
When would you ever /need/ to compare pointers to different objects?
For almost all C programmers, the answer is "never".
>
Sometimes, it is handy to encode certain conditions in pointers,
rather than having only a valid pointer or NULL. A compiler,
for example, might want to store the fact that an error occurred
while parsing a subexpression as a special pointer constant.
>
Compilers often have the unfair advantage, though, that they can
rely on what application programmers cannot, their implementation
details. (Some do not, such as f2c).
>
Standard library authors have the same superpowers, so that they can
implement an efficient memmove() even though a pure standard C
programmer cannot (other than by simply calling the standard library
memmove() function!).
>
This is more a symptom of bad ISA design/evolution than of libc
writers needing superpowers.
>
No, it is not. It has absolutely /nothing/ to do with the ISA.
>
For example, if ISA contains an MM instruction which is the
embodiment of memmove() then absolutely no heroics are needed
of desired in the libc call.
>
>
The existence of a dedicated assembly instruction does not let you write an efficient memmove() in standard C. That's why I said there was no connection between the two concepts.
>
For some targets, it can be helpful to write memmove() in assembly or using inline assembly, rather than in non-portable C (which is the common case).
>
Thus, it IS a symptom of ISA evolution that one has to rewrite
memmove() every time wider SIMD registers are available.
>
It is not that simple.
>
There can often be trade-offs between the speed of memmove() and memcpy() on large transfers, and the overhead in setting things up that is proportionally more costly for small transfers. Often that can be eliminated when the compiler optimises the functions inline - when the compiler knows the size of the move/copy, it can optimise directly.
>
What you are missing here David is the fact that Mitch's MM is a single instruction which does the entire memmove() operation, and has the inside knowledge about cache (residency at level x? width in bytes)/memory ranges/access rights/etc needed to do so in a very close to optimal manner, for both short and long transfers.
I am not missing that at all. And I agree that an advanced hardware MM instruction could be a very efficient way to implement both memcpy and memmove. (For my own kind of work, I'd worry about such looping instructions causing an unbounded increased in interrupt latency, but that too is solvable given enough hardware effort.)
And I agree that once you have an "MM" (or similar) instruction, you don't need to re-write the implementation for your memmove() and memcpy() library functions for every new generation of processors of a given target family.
What I /don't/ agree with is the claim that you /do/ need to keep re-writing your implementations all the time. You will /sometimes/ get benefits from doing so, but it is not as simple as Mitch made out.
>
I.e. totally removing the need for compiler tricks or wide register operations.
>
Also apropos the compiler library issue:
>
You start by teaching the compiler about the MM instruction, and to recognize common patterns (just as most compilers already do today), and then the memmove() calls will usually be inlined.
>
The original compile library issue was that it is impossible to write an efficient memmove() implementation using pure portable standard C. That is independent of any ISA, any specialist instructions for memory moves, and any compiler optimisations. And it is independent of the fact that some good compilers can inline at least some calls to memcpy() and memmove() today, using whatever instructions are most efficient for the target.
David, you and Mitch are among my most cherished writers here on c.arch, I really don't think any of us really disagree, it is just that we have been discussing two (mostly) orthogonal issues.
a) memmove/memcpy are so important that people have been spending a lot of time & effort trying to make it faster, with the complication that in general it cannot be implemented in pure C (which disallows direct comparison of arbitrary pointers).
b) Mitch have, like Andy ("Crazy") Glew many years before, realized that if a cpu architecture actually has an instruction designed to do this particular job, it behooves cpu architects to make sure that it is in fact so fast that it obviates any need for tricky coding to replace it.
Ideally, it should be able to copy a single object, up to a cache line in size, in the same or less time needed to do so manually with a SIMD 512-bit load followed by a 512-bit store (both ops masked to not touch anything it shouldn't)
REP MOVSB on x86 does the canonical memcpy() operation, originally by moving single bytes, and this was so slow that we also had REP MOVSW (moving 16-bit entities) and then REP MOVSD on the 386 and REP MOVSQ on 64-bit cpus.
With a suitable chunk of logic, the basic MOVSB operation could in fact handle any kinds of alignments and sizes, while doing the actual transfer at maximum bus speeds, i.e. at least one cache line/cycle for things already in $L1.
Terje
-- - <Terje.Mathisen at tmsw.no>"almost all programming can be viewed as an exercise in caching"
Date | Sujet | # | | Auteur |
16 Apr 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 237 | | Lawrence D'Oliveiro |
16 Apr 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 236 | | David Brown |
16 Apr 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | MitchAlsup1 |
26 May 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | MitchAlsup1 |
1 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 233 | | MitchAlsup1 |
1 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 232 | | Thomas Koenig |
1 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 225 | | MitchAlsup1 |
2 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 223 | | Brett |
3 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 222 | | Lawrence D'Oliveiro |
3 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Brett |
3 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Anton Ertl |
3 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 219 | | David Brown |
3 Oct 24 | Byte ordering (was: Whether something is RISC or not) | 218 | | Anton Ertl |
3 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 1 | | David Brown |
4 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 215 | | Lawrence D'Oliveiro |
4 Oct 24 | Re: Byte ordering | 1 | | Lynn Wheeler |
4 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 211 | | David Brown |
4 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 210 | | Anton Ertl |
4 Oct 24 | Re: Byte ordering | 5 | | BGB |
5 Oct 24 | Re: Byte ordering | 4 | | MitchAlsup1 |
5 Oct 24 | Re: Byte ordering | 2 | | BGB |
5 Oct 24 | Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
5 Oct 24 | Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
5 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 13 | | Lawrence D'Oliveiro |
5 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 12 | | Brett |
5 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 11 | | Anton Ertl |
5 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 10 | | Michael S |
6 Oct 24 | Re: Byte ordering | 1 | | Terje Mathisen |
6 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 8 | | Brett |
7 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 7 | | Lawrence D'Oliveiro |
7 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 6 | | Brett |
7 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 5 | | Michael S |
7 Oct 24 | Re: Byte ordering | 2 | | Stefan Monnier |
7 Oct 24 | Re: Byte ordering | 1 | | Michael S |
7 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 2 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: Byte ordering | 1 | | Terje Mathisen |
6 Oct 24 | Re: Byte ordering | 191 | | David Brown |
6 Oct 24 | Re: Byte ordering | 190 | | Anton Ertl |
6 Oct 24 | Re: Byte ordering | 189 | | John Dallman |
7 Oct 24 | Re: Byte ordering | 20 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: Byte ordering | 19 | | John Dallman |
9 Oct 24 | VMS/NT memory management (was: Byte ordering) | 1 | | Stefan Monnier |
15 Oct 24 | Re: Byte ordering | 2 | | Lawrence D'Oliveiro |
15 Oct 24 | Re: Byte ordering | 1 | | MitchAlsup1 |
15 Oct 24 | Re: Byte ordering | 15 | | Lawrence D'Oliveiro |
15 Oct 24 | Re: Byte ordering | 3 | | Michael S |
15 Oct 24 | Re: Byte ordering | 1 | | John Dallman |
18 Oct 24 | Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
15 Oct 24 | Re: Byte ordering | 9 | | John Dallman |
16 Oct 24 | Re: Byte ordering | 7 | | George Neuner |
16 Oct 24 | Re: Byte ordering | 6 | | Terje Mathisen |
16 Oct 24 | Re: Byte ordering | 5 | | David Brown |
17 Oct 24 | Re: Byte ordering | 2 | | George Neuner |
17 Oct 24 | Re: Byte ordering | 1 | | David Brown |
17 Oct 24 | Re: clouds, not Byte ordering | 2 | | John Levine |
17 Oct 24 | Re: clouds, not Byte ordering | 1 | | David Brown |
18 Oct 24 | Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
16 Oct 24 | Re: Byte ordering | 2 | | Paul A. Clayton |
18 Oct 24 | Re: Microkernels & Capabilities (was Re: Byte ordering) | 1 | | Lawrence D'Oliveiro |
7 Oct 24 | 80286 protected mode | 168 | | Anton Ertl |
7 Oct 24 | Re: 80286 protected mode | 5 | | Lars Poulsen |
7 Oct 24 | Re: 80286 protected mode | 4 | | Terje Mathisen |
7 Oct 24 | Re: 80286 protected mode | 1 | | Michael S |
7 Oct 24 | Re: 80286 protected mode | 2 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: 80286 protected mode | 1 | | Terje Mathisen |
7 Oct 24 | Re: 80286 protected mode | 3 | | Brett |
7 Oct 24 | Re: 80286 protected mode | 2 | | Michael S |
7 Oct 24 | Re: 80286 protected mode | 1 | | Brett |
7 Oct 24 | Re: 80286 protected mode | 1 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: 80286 protected mode | 152 | | MitchAlsup1 |
8 Oct 24 | Re: 80286 protected mode | 4 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: 80286 protected mode | 3 | | MitchAlsup1 |
9 Oct 24 | Re: 80286 protected mode | 1 | | David Brown |
15 Oct 24 | Re: 80286 protected mode | 1 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: 80286 protected mode | 147 | | Anton Ertl |
8 Oct 24 | Re: 80286 protected mode | 1 | | Robert Finch |
9 Oct 24 | Re: 80286 protected mode | 145 | | David Brown |
9 Oct 24 | Re: 80286 protected mode | 79 | | MitchAlsup1 |
9 Oct 24 | Re: 80286 protected mode | 78 | | David Brown |
9 Oct 24 | Re: 80286 protected mode | 77 | | Stephen Fuld |
10 Oct 24 | Re: 80286 protected mode | 2 | | MitchAlsup1 |
10 Oct 24 | Re: 80286 protected mode | 1 | | David Brown |
10 Oct 24 | Re: 80286 protected mode | 1 | | David Brown |
11 Oct 24 | Re: 80286 protected mode | 73 | | Tim Rentsch |
15 Oct 24 | Re: 80286 protected mode | 72 | | Stefan Monnier |
15 Oct 24 | Re: 80286 protected mode | 30 | | MitchAlsup1 |
16 Oct 24 | Re: 80286 protected mode | 25 | | MitchAlsup1 |
16 Oct 24 | Re: C and turtles, 80286 protected mode | 13 | | John Levine |
16 Oct 24 | Re: C and turtles, 80286 protected mode | 7 | | MitchAlsup1 |
16 Oct 24 | Re: C and turtles, 80286 protected mode | 6 | | John Levine |
17 Oct 24 | Re: C and turtles, 80286 protected mode | 5 | | Thomas Koenig |
20 Oct 24 | Re: C and turtles, 80286 protected mode | 4 | | Lawrence D'Oliveiro |
20 Oct 24 | Re: C and turtles, 80286 protected mode | 3 | | George Neuner |
22 Oct 24 | Re: C and turtles, 80286 protected mode | 2 | | Tim Rentsch |
22 Oct 24 | Re: C and turtles, 80286 protected mode | 1 | | George Neuner |
16 Oct 24 | Re: C and turtles, 80286 protected mode | 1 | | David Brown |
16 Oct 24 | Re: C and turtles, 80286 protected mode | 4 | | Paul A. Clayton |
17 Oct 24 | Re: C and turtles, 80286 protected mode | 1 | | David Brown |
20 Oct 24 | Re: C and turtles, 80286 protected mode | 2 | | Lawrence D'Oliveiro |
20 Oct 24 | Re: C and turtles, 80286 protected mode | 1 | | Paul A. Clayton |
16 Oct 24 | Re: 80286 protected mode | 7 | | Thomas Koenig |
17 Oct 24 | Re: 80286 protected mode | 3 | | George Neuner |
17 Oct 24 | Re: 80286 protected mode | 1 | | Tim Rentsch |
16 Oct 24 | Re: 80286 protected mode | 3 | | David Brown |
17 Oct 24 | Re: 80286 protected mode | 1 | | Tim Rentsch |
16 Oct 24 | Re: 80286 protected mode | 41 | | David Brown |
9 Oct 24 | Re: 80286 protected mode | 51 | | Thomas Koenig |
13 Oct 24 | Re: 80286 protected mode | 14 | | Anton Ertl |
8 Oct 24 | Re: 80286 protected mode | 6 | | John Levine |
6 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 2 | | Michael S |
4 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 1 | | John Dallman |
2 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Thomas Koenig |
2 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 5 | | David Schultz |
3 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Lawrence D'Oliveiro |