Sujet : Re: Misc: BGBCC targeting RV64G, initial results...
De : cr88192 (at) *nospam* gmail.com (BGB)
Groupes : comp.archDate : 17. Oct 2024, 01:03:26
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vepk8h$2f0m6$1@dont-email.me>
References : 1 2 3 4 5 6 7 8
User-Agent : Mozilla Thunderbird
On 10/16/2024 5:16 PM, MitchAlsup1 wrote:
On Wed, 16 Oct 2024 20:23:08 +0000, BGB wrote:
>
Ironically, one of the main arguable use-cases for old Fortran style IF
statements is implementing the binary dispatch logic in a binary
subdivided "switch()", but not enough to justify having a dedicated
instruction for it.
>
Say:
MOV Imm, Rt //pivot case
BLT Rt, Rx, .lbl_lo
BGT Rt, Rx, .lbl_hi
BRA .lbl_case
With a 64-bitinstruction one could do::
B3W .lbl_lo,.lbl_zero,.lbl_hi
rather straightforwardly.....
Possibly, but the harder part would be to deal with decoding and feeding the instruction through the pipeline.
Granted, I guess it could be decoded as if it were a normal 3RI op or similar, but then split up the immediate into multiple parts in EX1.
Say:
Decode as a 3RI Imm33s;
Then split the immediate into 3x 11-bits, calculate 3 offsets relative to PC, and apply the one which matches the result of the comparison (likely needing to route the S and Z flags from the subtract logic to EX1 or similar; vs the current logic routing the CMP T/F flag).
Could deal with the Branch PC as, say:
Calculate PC[47:16]+1, and PC[47:16]-1.
Calculate the low 16 bits of each branch direction;
Select direction based on branch result;
Select high bits of PC based on selected branch direction (-1, 0, 1).
But, worth the cost?...
This could mostly benefit programs that spend a significant part of their running time dispatching in sparse switch blocks, but probably not a lot else.
Disp11 couldn't deal with particularly large switch blocks, one might need a 96 bit encoding, possibly using 18 bits each, but this would be more expensive to deal with.
Or, 2-way with fall-through:
Rn>Rm: Branch High
Rn<Rm: Branch Low
Rm==Rn: Fall Through / No Branch
The fall-through case having a branch to the case label. This would allow 16 (2-way) and 20/23 bit displacements (for a plain JAL/BRA), so could deal with much bigger "switch()" blocks.
Would still need to think on this...
Date | Sujet | # | | Auteur |
27 Sep 24 | Misc: BGBCC targeting RV64G, initial results... | 37 | | BGB |
27 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 20 | | Robert Finch |
27 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 19 | | BGB |
27 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 18 | | MitchAlsup1 |
28 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 17 | | BGB |
28 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 16 | | MitchAlsup1 |
28 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 15 | | BGB |
29 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 14 | | MitchAlsup1 |
30 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 13 | | BGB |
30 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 1 | | MitchAlsup1 |
1 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 11 | | Robert Finch |
1 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 1 | | MitchAlsup1 |
3 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 9 | | BGB |
4 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 2 | | Robert Finch |
4 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 1 | | BGB |
6 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 6 | | MitchAlsup1 |
8 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 5 | | BGB |
8 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 4 | | MitchAlsup1 |
9 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 3 | | BGB |
9 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 1 | | Stefan Monnier |
9 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 1 | | MitchAlsup1 |
27 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 16 | | MitchAlsup1 |
27 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 2 | | BGB |
28 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 1 | | MitchAlsup1 |
28 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 13 | | Paul A. Clayton |
30 Sep 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 12 | | MitchAlsup1 |
16 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 11 | | Paul A. Clayton |
16 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 9 | | Stephen Fuld |
16 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 1 | | Thomas Koenig |
16 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 7 | | BGB |
17 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 6 | | MitchAlsup1 |
17 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 5 | | BGB |
18 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 4 | | MitchAlsup1 |
21 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 3 | | BGB |
21 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 2 | | MitchAlsup1 |
22 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 1 | | BGB |
16 Oct 24 | Re: Misc: BGBCC targeting RV64G, initial results... | 1 | | MitchAlsup1 |