Re: Retirement hobby (was Re: 80286 protected mode)

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Sujet : Re: Retirement hobby (was Re: 80286 protected mode)
De : tkoenig (at) *nospam* netcologne.de (Thomas Koenig)
Groupes : comp.arch
Date : 29. Oct 2024, 20:57:25
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vfren5$1mnvr$1@dont-email.me>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
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Terje Mathisen <terje.mathisen@tmsw.no> schrieb:
Thomas Koenig wrote:
EricP <ThatWouldBeTelling@thevillage.com> schrieb:
Thomas Koenig wrote:
MitchAlsup1 <mitchalsup@aol.com> schrieb:
>
In posits, a quire is an accumulator with as many binary digits
as to cover max-exponent to min-exponent; so one can accumulate
an essentially unbounded number of sums without loss of precision
--to obtain a sum with a single rounding.
>
Not restricted to posits, I believe (but the term may differ).
>
At university, I had my programming
courses on a Pascal compiler which implemented
https://en.wikipedia.org/wiki/Karlsruhe_Accurate_Arithmetic ,
a hardware implementation was on the 4361 as an option
https://en.wikipedia.org/wiki/IBM_4300#High-Accuracy_Arithmetic_Facility
>
These would be very large registers. You'd need some way to store and load
the these for register spills, fills and task switch, as well as move
and manage them.
>
Karlsruhe above has a link to
http://www.bitsavers.org/pdf/ibm/370/princOps/SA22-7093-0_High_Accuracy_Arithmetic_Jan84.pdf
>
which describes their large accumulators as residing in memory, which
avoids the spill/fill/switch issue but with an obvious performance hit:
>
"A floating-point accumulator occupies a 168-byte storage area that is
aligned on a 256-byte boundary. An accumulator consists of a four-byte
status area on the left, followed by a 164-byte numeric area."
>
The operands are specified by virtual address of their in-memory accumulator.
 
Makes sense, given the time this was implemented.  This was also a
mid-range machine, not a number cruncher.  I do not find the
number of cycles that the instructions took.
>
At the time, memory was just a few clock cycles away from the CPU, so
not really that problematic. Today, such a super-accumulator would stay
in $L1 most of the time, or at least the central, in-use cache line of
it, would do so.
>
 
But this was also for hex floating point.  A similar scheme for IEEE
double would need a bit more than 2048 bits, so five AVX-512 registers.
>
With 1312 bits of storage, their fp inputs (hex fp?) must have had a
smaller exponent range than ieee double.

IBM format had one sign bit, seven exponent bits and six or fourteen
hexadecimal digits for single and double precision, respectively.
(Insert fear and loathing for hex float here).

Date Sujet#  Auteur
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16 Apr 24 `* Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)236David Brown
16 Apr 24  +- Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)1MitchAlsup1
26 May 24  +- Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)1MitchAlsup1
1 Oct 24  `* Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)233MitchAlsup1
1 Oct 24   `* Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)232Thomas Koenig
1 Oct 24    +* Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)225MitchAlsup1
2 Oct 24    i+* Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)223Brett
3 Oct 24    ii`* Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)222Lawrence D'Oliveiro
3 Oct 24    ii +- Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)1Brett
3 Oct 24    ii +- Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)1Anton Ertl
3 Oct 24    ii `* Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)219David Brown
3 Oct 24    ii  `* Byte ordering (was: Whether something is RISC or not)218Anton Ertl
3 Oct 24    ii   +- Re: Byte ordering (was: Whether something is RISC or not)1David Brown
4 Oct 24    ii   +* Re: Byte ordering (was: Whether something is RISC or not)215Lawrence D'Oliveiro
4 Oct 24    ii   i+- Re: Byte ordering1Lynn Wheeler
4 Oct 24    ii   i+* Re: Byte ordering (was: Whether something is RISC or not)211David Brown
4 Oct 24    ii   ii`* Re: Byte ordering (was: Whether something is RISC or not)210Anton Ertl
4 Oct 24    ii   ii +* Re: Byte ordering5BGB
5 Oct 24    ii   ii i`* Re: Byte ordering4MitchAlsup1
5 Oct 24    ii   ii i +* Re: Byte ordering2BGB
5 Oct 24    ii   ii i i`- Re: Byte ordering1Lawrence D'Oliveiro
5 Oct 24    ii   ii i `- Re: Byte ordering1Lawrence D'Oliveiro
5 Oct 24    ii   ii +* Re: Byte ordering (was: Whether something is RISC or not)13Lawrence D'Oliveiro
5 Oct 24    ii   ii i`* Re: Byte ordering (was: Whether something is RISC or not)12Brett
5 Oct 24    ii   ii i `* Re: Byte ordering (was: Whether something is RISC or not)11Anton Ertl
5 Oct 24    ii   ii i  `* Re: Byte ordering (was: Whether something is RISC or not)10Michael S
6 Oct 24    ii   ii i   +- Re: Byte ordering1Terje Mathisen
6 Oct 24    ii   ii i   `* Re: Byte ordering (was: Whether something is RISC or not)8Brett
7 Oct 24    ii   ii i    `* Re: Byte ordering (was: Whether something is RISC or not)7Lawrence D'Oliveiro
7 Oct 24    ii   ii i     `* Re: Byte ordering (was: Whether something is RISC or not)6Brett
7 Oct 24    ii   ii i      `* Re: Byte ordering (was: Whether something is RISC or not)5Michael S
7 Oct 24    ii   ii i       +* Re: Byte ordering2Stefan Monnier
7 Oct 24    ii   ii i       i`- Re: Byte ordering1Michael S
7 Oct 24    ii   ii i       `* Re: Byte ordering (was: Whether something is RISC or not)2Lawrence D'Oliveiro
8 Oct 24    ii   ii i        `- Re: Byte ordering1Terje Mathisen
6 Oct 24    ii   ii `* Re: Byte ordering191David Brown
6 Oct 24    ii   ii  `* Re: Byte ordering190Anton Ertl
6 Oct 24    ii   ii   `* Re: Byte ordering189John Dallman
7 Oct 24    ii   ii    +* Re: Byte ordering20Lawrence D'Oliveiro
8 Oct 24    ii   ii    i`* Re: Byte ordering19John Dallman
9 Oct 24    ii   ii    i +- VMS/NT memory management (was: Byte ordering)1Stefan Monnier
15 Oct 24    ii   ii    i +* Re: Byte ordering2Lawrence D'Oliveiro
15 Oct 24    ii   ii    i i`- Re: Byte ordering1MitchAlsup1
15 Oct 24    ii   ii    i `* Re: Byte ordering15Lawrence D'Oliveiro
15 Oct 24    ii   ii    i  +* Re: Byte ordering3Michael S
15 Oct 24    ii   ii    i  i+- Re: Byte ordering1John Dallman
18 Oct 24    ii   ii    i  i`- Re: Byte ordering1Lawrence D'Oliveiro
15 Oct 24    ii   ii    i  +* Re: Byte ordering9John Dallman
16 Oct 24    ii   ii    i  i+* Re: Byte ordering7George Neuner
16 Oct 24    ii   ii    i  ii`* Re: Byte ordering6Terje Mathisen
16 Oct 24    ii   ii    i  ii `* Re: Byte ordering5David Brown
17 Oct 24    ii   ii    i  ii  +* Re: Byte ordering2George Neuner
17 Oct 24    ii   ii    i  ii  i`- Re: Byte ordering1David Brown
17 Oct 24    ii   ii    i  ii  `* Re: clouds, not Byte ordering2John Levine
17 Oct 24    ii   ii    i  ii   `- Re: clouds, not Byte ordering1David Brown
18 Oct 24    ii   ii    i  i`- Re: Byte ordering1Lawrence D'Oliveiro
16 Oct 24    ii   ii    i  `* Re: Byte ordering2Paul A. Clayton
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7 Oct 24    ii   ii     +* Re: 80286 protected mode5Lars Poulsen
7 Oct 24    ii   ii     i`* Re: 80286 protected mode4Terje Mathisen
7 Oct 24    ii   ii     i +- Re: 80286 protected mode1Michael S
7 Oct 24    ii   ii     i `* Re: 80286 protected mode2Lawrence D'Oliveiro
8 Oct 24    ii   ii     i  `- Re: 80286 protected mode1Terje Mathisen
7 Oct 24    ii   ii     +* Re: 80286 protected mode3Brett
7 Oct 24    ii   ii     i`* Re: 80286 protected mode2Michael S
7 Oct 24    ii   ii     i `- Re: 80286 protected mode1Brett
7 Oct 24    ii   ii     +- Re: 80286 protected mode1Lawrence D'Oliveiro
8 Oct 24    ii   ii     +* Re: 80286 protected mode152MitchAlsup1
8 Oct 24    ii   ii     i+* Re: 80286 protected mode4Lawrence D'Oliveiro
8 Oct 24    ii   ii     ii`* Re: 80286 protected mode3MitchAlsup1
9 Oct 24    ii   ii     ii +- Re: 80286 protected mode1David Brown
15 Oct 24    ii   ii     ii `- Re: 80286 protected mode1Lawrence D'Oliveiro
8 Oct 24    ii   ii     i`* Re: 80286 protected mode147Anton Ertl
8 Oct 24    ii   ii     i +- Re: 80286 protected mode1Robert Finch
9 Oct 24    ii   ii     i `* Re: 80286 protected mode145David Brown
9 Oct 24    ii   ii     i  +* Re: 80286 protected mode79MitchAlsup1
9 Oct 24    ii   ii     i  i`* Re: 80286 protected mode78David Brown
9 Oct 24    ii   ii     i  i `* Re: 80286 protected mode77Stephen Fuld
10 Oct 24    ii   ii     i  i  +* Re: 80286 protected mode2MitchAlsup1
10 Oct 24    ii   ii     i  i  i`- Re: 80286 protected mode1David Brown
10 Oct 24    ii   ii     i  i  +- Re: 80286 protected mode1David Brown
11 Oct 24    ii   ii     i  i  `* Re: 80286 protected mode73Tim Rentsch
15 Oct 24    ii   ii     i  i   `* Re: 80286 protected mode72Stefan Monnier
15 Oct 24    ii   ii     i  i    +* Re: 80286 protected mode30MitchAlsup1
16 Oct 24    ii   ii     i  i    i+* Re: 80286 protected mode25MitchAlsup1
16 Oct 24    ii   ii     i  i    ii+* Re: C and turtles, 80286 protected mode13John Levine
16 Oct 24    ii   ii     i  i    iii+* Re: C and turtles, 80286 protected mode7MitchAlsup1
16 Oct 24    ii   ii     i  i    iiii`* Re: C and turtles, 80286 protected mode6John Levine
17 Oct 24    ii   ii     i  i    iiii `* Re: C and turtles, 80286 protected mode5Thomas Koenig
20 Oct 24    ii   ii     i  i    iiii  `* Re: C and turtles, 80286 protected mode4Lawrence D'Oliveiro
20 Oct 24    ii   ii     i  i    iiii   `* Re: C and turtles, 80286 protected mode3George Neuner
22 Oct 24    ii   ii     i  i    iiii    `* Re: C and turtles, 80286 protected mode2Tim Rentsch
22 Oct 24    ii   ii     i  i    iiii     `- Re: C and turtles, 80286 protected mode1George Neuner
16 Oct 24    ii   ii     i  i    iii+- Re: C and turtles, 80286 protected mode1David Brown
16 Oct 24    ii   ii     i  i    iii`* Re: C and turtles, 80286 protected mode4Paul A. Clayton
17 Oct 24    ii   ii     i  i    iii +- Re: C and turtles, 80286 protected mode1David Brown
20 Oct 24    ii   ii     i  i    iii `* Re: C and turtles, 80286 protected mode2Lawrence D'Oliveiro
20 Oct 24    ii   ii     i  i    iii  `- Re: C and turtles, 80286 protected mode1Paul A. Clayton
16 Oct 24    ii   ii     i  i    ii+* Re: 80286 protected mode7Thomas Koenig
17 Oct 24    ii   ii     i  i    ii+* Re: 80286 protected mode3George Neuner
17 Oct 24    ii   ii     i  i    ii`- Re: 80286 protected mode1Tim Rentsch
16 Oct 24    ii   ii     i  i    i+* Re: 80286 protected mode3David Brown
17 Oct 24    ii   ii     i  i    i`- Re: 80286 protected mode1Tim Rentsch
16 Oct 24    ii   ii     i  i    `* Re: 80286 protected mode41David Brown
9 Oct 24    ii   ii     i  +* Re: 80286 protected mode51Thomas Koenig
13 Oct 24    ii   ii     i  `* Re: 80286 protected mode14Anton Ertl
8 Oct 24    ii   ii     `* Re: 80286 protected mode6John Levine
6 Oct 24    ii   i`* Re: Byte ordering (was: Whether something is RISC or not)2Michael S
4 Oct 24    ii   `- Re: Byte ordering (was: Whether something is RISC or not)1John Dallman
2 Oct 24    i`- Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)1Thomas Koenig
2 Oct 24    +* Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)5David Schultz
3 Oct 24    `- Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)1Lawrence D'Oliveiro

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