Page fetching cache controller

Thinking about organizing a cache controller to fetch an entire 4kB page of memory at a time on a cache miss. The reason being the memory system is tremendously faster than the CPU clock as long as burst mode is used. The longer the burst, the better. The entire 4kB page can be transferred in < 40 CPU clocks. It takes about 4 CPU clocks to fetch one cache line. Cache is still needed as the memory latency prevents its direct use.