Sujet : Re: Reverse engineering of Intel branch predictors
De : tkoenig (at) *nospam* netcologne.de (Thomas Koenig)
Groupes : comp.archDate : 13. Nov 2024, 21:54:56
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vh33n0$2crf1$1@dont-email.me>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13
User-Agent : slrn/1.0.3 (Linux)
Stefan Monnier <
monnier@iro.umontreal.ca> schrieb:
If you consider the two levels of language at play (the CPU view
at the level of machine language and the interpreter's view of the
bytecode language), IIUC the branch history of the CPU view ends up
being a usable approximation of the bytecode-level instruction pointer,
so for those sections of your bytecode-level program which are sufficiently
repetitive, the prediction applied by the CPU can correctly predict the
next bytecode.
To me, that looks like the bytecode is insufficiently expressive, if
an often-repeating sequence occurs :-)
In the presence of a good predictor, it would still be an interesting
question if a more compressed version would actually perform better.