Re: portable proxy collector test...

On 12/9/24 07:28, jseigh wrote:

On 12/8/24 18:31, Chris M. Thomasson wrote:

Well, for a ARM64 gcc 14.2.0 a relaxed fetch_add I get __aarch64_ldadd8_acq_rel in the asm.
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https://godbolt.org/z/YzPdM8j33
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acq_rel barrier for a relaxed membar? Well, that makes me go grrrrrr!
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It has to be akin to the LOCK prefix over on x86. I want it relaxed damn it! ;^)

 Apart of the memory ordering, if you are using atomic_fetch_add you
are going to get an interlocked instruction which is probably
overkill and has more overhead than you want.   Atomic ops
assume other cpus might be trying atomic rmw ops on other
cpus which is not the case for userspace rcu.  You want
an atomic relaxed load, and atomic relaxed store of the
incrmented value.  It will be faster.
 

I should add, you will need a store/load memory barrier
after that unless you use an asymetric memory barrier.
I haven't worked that logic out yet since I'm not working
on any userspace RCU (qsbr) implementations. Probably
the same number of grace periods.