Re: What do we call non-pipelined designs?

On 2024-12-08 5:10 p.m., Marcus wrote:

I usually (and simplistically) divide CPU designs (implementations) into
two main categories:
 - Pipelined
- Non-pipelined
 Of course, there is a sliding scale at play, but let's not get into that
debate.
 My question is: What is the best name for non-pipelined designs?
 I'm thinking about CPU:s that transition through several states (one
clock cycle after another) when executing a single instruction (e.g.
FETCH + DECODE + EXECUTE), and where instruction and data typically
share the same memory interface.
 /Marcus

According to my understanding of  “pipelined” most designs are pipelined. There are not very many non-pipelined designs. Non-pipelined designs perform everything in one long clock cycle. Otherwise, there are two major classes of pipelined designs, non-overlapped pipeline and overlapped pipeline. Some designs are partially overlapped pipelined.