Re: Cost of handling misaligned access

On 2/2/2025 12:10 PM, Thomas Koenig wrote:

Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
 

The OS must also be able to keep both pages in physical memory until
the access is complete, or there will be no progress.  Should not be a
problem these days, but the 48 pages or so potentially needed by VAX
complicated the OS.

 48 pages?  What instruction would need that?

Hmm...
I ended up with a 4-way set associative TLB as it ended up being needed to avoid the CPU getting stuck in a TLB-miss loop in the worst-case scenario:
An instruction fetch where the line-pair crosses a page boundary (and L1 I$ misses) for an instruction accessing a memory address where the line-pair also crosses a page boundary (and the L1 D$ misses).
One can almost get away with two-way, except that almost inevitably the CPU would encounter and get stuck in an infinite TLB miss loop (despite the seeming rarity, happens roughly once every few seconds or so).
...