Re: Why VAX Was the Ultimate CISC and Not RISC

On 2025-03-07 12:34 p.m., MitchAlsup1 wrote:

On Fri, 7 Mar 2025 11:08:56 +0000, BGB wrote:
 

On 3/6/2025 10:09 PM, Lawrence D'Oliveiro wrote:

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>
So, writing things like:
   y[55:48]=x[19:12];

 2 instructions in My 66000. One extract, one insert.

Ibid for Q+. The logic for an extract and insert as one operation might add to the timing. Extract, sign/zero extend and copy back. Fields may be different sizes.

 

>
And:
   j=x[19:12];
Also a single instruction, or 2 or 3 in the fallback case (encoded as a
shift and mask).

 1 instruction--extract (SLL or SLA)

Q+ has EXT/EXTU which is basically a SRL or SRA with mask applied afterwards. PowerPC has a rotate-left-and-mask instruction. In my opinion it makes more sense for extracts to be shifting right.
Not sure yet how this will be handled in Q+2. SRLPAM (shift right pair and mask), but I ran out of opcode bits. There are only four bits available to represent the mask field, but a 15-bit wide field might be enough to be useful most of the time. Can always code more than one instruction to get beyond 15 bits.

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>
For a simple test:
   lj[ 7: 0]=li[31:24];
   lj[15: 8]=li[23:16];
   lj[23:16]=li[15: 8];
   lj[31:24]=li[ 7: 0];
Does seem to compile down to 4 instructions.

Some work in the peephole optimizer might be able to reduce this.

 1 innstruction:: BITR rd,rs1,<8>
 

Though, looking at the compiler code, it would be subject to the "side
effects in lvalue may be applied twice" bug:
   (*ct++)[19:12]=(*cs++)[15:8];

 5 instructions:: LD, LD, EXT, INS, ST; with deferred ADD to Rcs and Rct.