Re: MSI interrupts

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Sujet : Re: MSI interrupts
De : cross (at) *nospam* spitfire.i.gajendra.net (Dan Cross)
Groupes : comp.arch
Date : 28. Mar 2025, 03:53:57
Autres entêtes
Organisation : PANIX Public Access Internet and UNIX, NYC
Message-ID : <vs5305$rd4$1@reader1.panix.com>
References : 1 2 3 4
User-Agent : trn 4.0-test77 (Sep 1, 2010)
In article <34434320650f5844b18b1c0b684acf43@www.novabbs.org>,
MitchAlsup1 <mitchalsup@aol.com> wrote:
On Thu, 27 Mar 2025 17:19:21 +0000, Dan Cross wrote:
In article <7a093bbb356e3bda3782c15ca27e98a7@www.novabbs.org>,
MitchAlsup1 <mitchalsup@aol.com> wrote:
-------------------
Or maybe even just swapping places between two elements in a
linked list.  For example:
>
void
swap_places(Node **head, Node *a, Node *b)
{
        Node *hp, *an, *ap, *bn, *bp;
>
        assert(head != NULL);
        assert(a != NULL);
        assert(b != NULL);
>
        if (a == b)
                return;
>
  esmLOCKprefetch(*head);
>
This should be a load not prefetch--you want the value of *head

I wondered about that.  I ASSumed that `esmLOCKprefetch` was
enough to set up a cache line address monitor on `*head`, but if
you tell me I need `esmLOCKload`, then I need `esmLOCKload`:

hp = esmLOCKload(*head);
if (hp == a)
*head = b;  // Note I need to set whatever head points to, not hp.
else if (hp == b)
*head = a;

(You can see a vestige of me trying that earlier by the `hp`
temporary that I left in when I posted that initially, but I
didn't like how it looked, so I changed it to what was posted.)

        if (*head == a) // see !
                *head = b;
        else if (*head == b)
                *head = a;
>
There is a ESM rule that states:: all participating cache lines
must be touched before any participating cache lines can be
modified.

Are these rules in a reference somewhere I can see?  I kinda
reckoned `esmLOCKprefetch` would be enough to "touch" the line,
but I fully admit I was just guessing.  Looks like `prefetch` is
mostly for the case where you'll store, but don't need to read?

Also note: Participating cache lines are checked for write permission
at touch time, and on cache miss, read with intent to modify.

Ok.

        an = esmLOCKload(a->next);
        ap = esmLOCKload(a->prev);
        bn = esmLOCKload(b->next);
        bp = esmLOCKload(b->prev);
>
        b->next = an;
        if (an != NULL) {
                esmLOCKprefetch(an->prev);
                an->prev = b;
}
        b->prev = ap;
        if (ap != NULL) {
                esmLOCKprefetch(ap->next);
                ap->next = b;
}
>
        a->next = bn;
        if (bn != NULL) {
esmLOCKprefetch(bn->prev);
                bn->prev = a;
}
        if (bp != NULL) {
        esmLOCKprefetch(bp->next);
                bp->next = a;
}
        esmLOCKstore(a->prev, bp);
}
>
What I think you want:: (ignoring the 9 participants limit)

You mean 8 participants limit?  That counting thing again.  ;-}

What I really wanted was an example that exceeded that limit as
an expository vehicle for understanding what happens when the
limit is exceeded.  What does the hardware do in that case?

void
swap_places(Node **head, Node *a, Node *b)
{
        Node *hp, *an, *ap, *bn, *bp;
>
        assert(head != NULL);
        assert(a != NULL);
        assert(b != NULL);
>
        if (a == b)
                return;
>
top_of_ATOMIC_event:
>
// this is the recovery point is you don't use esmINTERFERENCE()
// the very next instruction begins the event.

Yup.  Tracking.

        esmLOCKprefetch( an = esmLOCKload(a->next) );
        esmLOCKprefetch( ap = esmLOCKload(a->prev) );
        esmLOCKprefetch( bn = esmLOCKload(b->next) );
        esmLOCKprefetch( bp = esmLOCKload(b->prev) );

What exactly does this do?  This "touches" whatever lines the
things that `an`, `ap`, `bn`, and `bp` are all in, as well as
the lines that the `a` and `b` prev and next pointers point
into as well, right?

  Node *Ehead = esmLOCKload(*head);

You shoulda just used the `hp` local I left for you for exactly
this.  :-D

// by placing all the the touching before any manifestation, you put
// all the touch latency* in the code before it has tried to damage any
// participating memory location. (*) and TLB latency and 2nd party
// observation of your event.
>
// this would be the point where you would insert if( esmINTERFERENCE(
))
// if you wanted control at a known failure point rather than at the
// top of the event on failure.
>
        if (Ehead == a)
                *head = b;
        else if (Ehead == b)
                *head = a;
>
        b->next = an;
        if (an != NULL) {
                an->prev = b;
}
        b->prev = ap;
        if (ap != NULL) {
                ap->next = b;
}
>
        a->next = bn;
        if (bn != NULL) {
                bn->prev = a;
}
        if (bp != NULL) {
                bp->next = a;
}
        esmLOCKstore(a->prev, bp);
}
>
// now manifestation has lowest possible latency (as seen by this core
alone)

Doesn't this code now assume that `an->prev` is in the same
cache line as `an`, and similarly that `bn` is in the same line
as `bn->prev`? Absent an alignment constraint on the `Node`
type, that's not guaranteed given the definition posted earlier.

That may be an odd and ill-advised thing for a programmer to do
if they want their list type to work with atomic events, but it
is possible.

The node pointers and their respective `next` pointers are okay,
so I wonder if perhaps this might have been written as:

void
swap_places(Node **head, Node *a, Node *b)
{
        Node *hp, *an, *ap, *bn, *bp;

        assert(head != NULL);
        assert(a != NULL);
        assert(b != NULL);

        if (a == b)
                return;

        hp = esmLOCKload(*head);
        esmLOCKprefetch(an = esmLOCKload(a->next));
        ap = esmLOCKload(a->prev);
        esmLOCKprefetch(bn = esmLOCKload(b->next));
        bp = esmLOCKload(b->prev);

        if (an != NULL)
                esmLOCKprefetch(an->prev);
        if (bn != NULL) {
                esmLOCKprefetch(bn->prev);
bn->prev = a;
        }

        if (hp == a)
                *head = b;
        else if (hp == b)
                *head = a;

        b->next = an;
        if (an != NULL)
                an->prev = b;
        b->prev = ap;
        if (ap != NULL)
                ap->next = b;

        a->next = bn;
        if (bp != NULL)
                bp->next = a;

        esmLOCKstore(a->prev, bp);
}

But now the conditional testing whether or not `an` is `NULL` is
repeated.  Is the additional branch overhead worth it here?

- Dan C.


Date Sujet#  Auteur
13 Mar 25 * MSI interrupts163Robert Finch
13 Mar 25 `* Re: MSI interrupts162MitchAlsup1
13 Mar 25  +* Re: MSI interrupts5Robert Finch
13 Mar 25  i+- Re: MSI interrupts1MitchAlsup1
13 Mar 25  i`* Re: MSI interrupts3Robert Finch
13 Mar 25  i +- Re: MSI interrupts1MitchAlsup1
13 Mar 25  i `- Re: MSI interrupts1Stefan Monnier
13 Mar 25  `* Re: MSI interrupts156MitchAlsup1
13 Mar 25   `* Re: MSI interrupts155MitchAlsup1
14 Mar 25    `* Re: MSI interrupts154MitchAlsup1
14 Mar 25     `* Re: MSI interrupts153MitchAlsup1
14 Mar 25      `* Re: MSI interrupts152MitchAlsup1
15 Mar 25       `* Re: MSI interrupts151Robert Finch
15 Mar 25        `* Re: MSI interrupts150MitchAlsup1
15 Mar 25         `* Re: MSI interrupts149Robert Finch
15 Mar 25          `* Re: MSI interrupts148MitchAlsup1
16 Mar 25           `* Re: MSI interrupts147Robert Finch
16 Mar 25            +- Re: MSI interrupts1MitchAlsup1
17 Mar 25            +* Re: MSI interrupts142Michael S
17 Mar 25            i+- Re: MSI interrupts1Robert Finch
17 Mar 25            i+* Re: MSI interrupts133Robert Finch
18 Mar 25            ii+* Re: MSI interrupts127Robert Finch
19 Mar 25            iii+* Re: MSI interrupts124MitchAlsup1
19 Mar 25            iiii+* Re: MSI interrupts121Dan Cross
19 Mar 25            iiiii+* Re: MSI interrupts112MitchAlsup1
20 Mar 25            iiiiii`* Re: MSI interrupts111Dan Cross
20 Mar 25            iiiiii `* Re: MSI interrupts110MitchAlsup1
20 Mar 25            iiiiii  `* Re: MSI interrupts109Dan Cross
20 Mar 25            iiiiii   +* Re: MSI interrupts31MitchAlsup1
24 Mar 25            iiiiii   i`* Re: MSI interrupts30Dan Cross
24 Mar 25            iiiiii   i +* Re: MSI interrupts20MitchAlsup1
24 Mar 25            iiiiii   i i+* Re: MSI interrupts18Stefan Monnier
24 Mar 25            iiiiii   i ii`* Re: MSI interrupts17MitchAlsup1
24 Mar 25            iiiiii   i ii `* Re: MSI interrupts16Dan Cross
24 Mar 25            iiiiii   i ii  +* Re: MSI interrupts8MitchAlsup1
25 Mar 25            iiiiii   i ii  i`* Re: MSI interrupts7Dan Cross
25 Mar 25            iiiiii   i ii  i `* Re: MSI interrupts6Dan Cross
25 Mar 25            iiiiii   i ii  i  `* Re: MSI interrupts5Stefan Monnier
25 Mar 25            iiiiii   i ii  i   +- Re: MSI interrupts1Stefan Monnier
25 Mar 25            iiiiii   i ii  i   +- Re: MSI interrupts1Dan Cross
27 Mar 25            iiiiii   i ii  i   `* Re: MSI interrupts2Terje Mathisen
27 Mar 25            iiiiii   i ii  i    `- Re: MSI interrupts1MitchAlsup1
25 Mar 25            iiiiii   i ii  `* Re: MSI interrupts7Chris M. Thomasson
25 Mar 25            iiiiii   i ii   `* Re: MSI interrupts6Dan Cross
25 Mar 25            iiiiii   i ii    `* Re: MSI interrupts5Chris M. Thomasson
25 Mar 25            iiiiii   i ii     `* Re: MSI interrupts4Dan Cross
26 Mar 25            iiiiii   i ii      `* Re: MSI interrupts3Chris M. Thomasson
26 Mar 25            iiiiii   i ii       `* Re: MSI interrupts2Dan Cross
26 Mar 25            iiiiii   i ii        `- Re: MSI interrupts1Chris M. Thomasson
24 Mar 25            iiiiii   i i`- Re: MSI interrupts1Dan Cross
24 Mar 25            iiiiii   i +- Re: MSI interrupts1MitchAlsup1
24 Mar 25            iiiiii   i `* Re: MSI interrupts8Dan Cross
24 Mar 25            iiiiii   i  `* Re: MSI interrupts7Chris M. Thomasson
24 Mar 25            iiiiii   i   `* Re: MSI interrupts6Dan Cross
25 Mar 25            iiiiii   i    `* Re: MSI interrupts5Chris M. Thomasson
25 Mar 25            iiiiii   i     +* Re: MSI interrupts2Chris M. Thomasson
25 Mar 25            iiiiii   i     i`- Re: MSI interrupts1Dan Cross
25 Mar 25            iiiiii   i     `* Re: MSI interrupts2Dan Cross
25 Mar 25            iiiiii   i      `- Re: MSI interrupts1Chris M. Thomasson
24 Mar 25            iiiiii   +- Re: MSI interrupts1Chris M. Thomasson
24 Mar 25            iiiiii   `* Re: MSI interrupts76Dan Cross
24 Mar 25            iiiiii    +* Re: MSI interrupts57MitchAlsup1
25 Mar 25            iiiiii    i`* Re: MSI interrupts56Dan Cross
25 Mar 25            iiiiii    i `* Re: MSI interrupts55MitchAlsup1
25 Mar 25            iiiiii    i  +* Re: MSI interrupts2Stefan Monnier
25 Mar 25            iiiiii    i  i`- Re: MSI interrupts1Chris M. Thomasson
25 Mar 25            iiiiii    i  +- Re: MSI interrupts1Dan Cross
25 Mar 25            iiiiii    i  `* Re: MSI interrupts51MitchAlsup1
25 Mar 25            iiiiii    i   `* Re: MSI interrupts50Dan Cross
25 Mar 25            iiiiii    i    `* Re: MSI interrupts49MitchAlsup1
25 Mar 25            iiiiii    i     `* Re: MSI interrupts48Dan Cross
25 Mar 25            iiiiii    i      `* Re: MSI interrupts47MitchAlsup1
25 Mar 25            iiiiii    i       `* Re: MSI interrupts46Dan Cross
25 Mar 25            iiiiii    i        +* Re: MSI interrupts8Stefan Monnier
26 Mar 25            iiiiii    i        i+* Re: MSI interrupts5Dan Cross
26 Mar 25            iiiiii    i        ii`* Re: MSI interrupts4Stefan Monnier
26 Mar 25            iiiiii    i        ii +- Re: MSI interrupts1Dan Cross
26 Mar 25            iiiiii    i        ii `* Re: MSI interrupts2MitchAlsup1
27 Mar 25            iiiiii    i        ii  `- Re: MSI interrupts1Stefan Monnier
26 Mar 25            iiiiii    i        i+- Re: MSI interrupts1Chris M. Thomasson
26 Mar 25            iiiiii    i        i`- Re: MSI interrupts1MitchAlsup1
26 Mar 25            iiiiii    i        `* Re: MSI interrupts37MitchAlsup1
26 Mar 25            iiiiii    i         `* Re: MSI interrupts36Dan Cross
26 Mar 25            iiiiii    i          +* Re: MSI interrupts4Stefan Monnier
26 Mar 25            iiiiii    i          i`* Re: MSI interrupts3Dan Cross
26 Mar 25            iiiiii    i          i `* Re: MSI interrupts2Chris M. Thomasson
4 Apr 25            iiiiii    i          i  `- Re: MSI interrupts1Chris M. Thomasson
26 Mar 25            iiiiii    i          `* Re: MSI interrupts31MitchAlsup1
26 Mar 25            iiiiii    i           +- Re: MSI interrupts1Stefan Monnier
26 Mar 25            iiiiii    i           +* Re: MSI interrupts2Stefan Monnier
27 Mar 25            iiiiii    i           i`- Re: MSI interrupts1MitchAlsup1
27 Mar 25            iiiiii    i           +* Re: MSI interrupts3MitchAlsup1
27 Mar 25            iiiiii    i           i`* Re: MSI interrupts2MitchAlsup1
27 Mar 25            iiiiii    i           i `- Re: MSI interrupts1Dan Cross
27 Mar 25            iiiiii    i           `* Re: MSI interrupts24Dan Cross
27 Mar 25            iiiiii    i            +* Re: MSI interrupts2Stefan Monnier
27 Mar 25            iiiiii    i            i`- Re: MSI interrupts1Dan Cross
27 Mar 25            iiiiii    i            +* Re: MSI interrupts12MitchAlsup1
28 Mar 25            iiiiii    i            i`* Re: MSI interrupts11Dan Cross
28 Mar 25            iiiiii    i            i +- Re: MSI interrupts1MitchAlsup1
28 Mar 25            iiiiii    i            i +* Re: MSI interrupts5MitchAlsup1
28 Mar 25            iiiiii    i            i +* Re: MSI interrupts2Stefan Monnier
28 Mar 25            iiiiii    i            i `* Re: MSI interrupts2Chris M. Thomasson
27 Mar 25            iiiiii    i            `* Re: MSI interrupts9MitchAlsup1
25 Mar 25            iiiiii    `* Re: MSI interrupts18Dan Cross
20 Mar 25            iiiii`* Re: MSI interrupts8MitchAlsup1
19 Mar 25            iiii`* Re: MSI interrupts2MitchAlsup1
19 Mar 25            iii`* Re: MSI interrupts2Robert Finch
18 Mar 25            ii`* Re: MSI interrupts5MitchAlsup1
17 Mar 25            i`* Re: MSI interrupts7MitchAlsup1
17 Mar 25            `* Re: MSI interrupts3Robert Finch

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