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I have several examples where My 66000 with only 32-GPRs compilesStark uses a four bit code to encode where on the cache line a large constant is located. The assembler just piles them up at the end of the cache line. Sometimes space is wasted if an instruction with a constant will not fit on the cache line. I think it is <6%. It has got to be close to the finagling that RISCV does for larger constants.
to fewer instructions than RISC-V with 32+32 registers.
I have other examples where My 66000 does not need spill/fill code
and RISC-V does, too.
>Universal constants also reduces pressure both on ISA on the GPRs, and
I like having the extra register files, it is just a personal
programming convenience. It reduces the pressure on the general-purpose
register file.
on executing instructions.
Changing the capital R in RISC into a lower case r ?!?Lower case r?
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