Re: auto predicating branches

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Sujet : Re: auto predicating branches
De : robfi680 (at) *nospam* gmail.com (Robert Finch)
Groupes : comp.arch
Date : 21. Apr 2025, 02:26:53
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vu46su$1170i$1@dont-email.me>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
User-Agent : Mozilla Thunderbird
On 2025-04-20 2:44 a.m., Robert Finch wrote:
>
I have several examples where My 66000 with only 32-GPRs compiles
to fewer instructions than RISC-V with 32+32 registers.
>
I have other examples where My 66000 does not need spill/fill code
and RISC-V does, too.
>
>
I like having the extra register files, it is just a personal
programming convenience. It reduces the pressure on the general-purpose
register file.
>
Universal constants also reduces pressure both on ISA on the GPRs, and
on executing instructions.
 Stark uses a four bit code to encode where on the cache line a large constant is located. The assembler just piles them up at the end of the cache line. Sometimes space is wasted if an instruction with a constant will not fit on the cache line. I think it is <6%. It has got to be close to the finagling that RISCV does for larger constants.
>
>
Changing the capital R in RISC into a lower case r ?!?
 Lower case r?
 Been working on predicate logic tonight. Predicate shadow is limited to six instruction due to a limited mask size. Can always code more of the same predicate to skip more instructions.
 I have the code searching the ROB backwards until a predicate instruction is encountered, to determine if there is a predicate. Searching fewer instructions helps. Probably not the cleverest way of doing things, sort of brute force.
Got hung up on the predicate logic and decided to tackle something easier but similar. Having branches automatically convert into predicates when they branch forward a short distance <7 instructions. The instructions are likely already in the pipeline since it is only one or two instruction groups.
Ran into issues with the predicate logic and the LOC were just exploding. Better to work on improving the branches first, predicates might fall out later.

Date Sujet#  Auteur
4 Oct 24 * Re: Tonights Tradeoff - Background Execution Buffers78Robert Finch
4 Oct 24 +* Re: Tonights Tradeoff - Background Execution Buffers75Anton Ertl
4 Oct 24 i`* Re: Tonights Tradeoff - Background Execution Buffers74Robert Finch
5 Oct 24 i `* Re: Tonights Tradeoff - Background Execution Buffers73Anton Ertl
9 Oct 24 i  `* Re: Tonights Tradeoff - Background Execution Buffers72Robert Finch
9 Oct 24 i   +* Re: Tonights Tradeoff - Background Execution Buffers3MitchAlsup1
9 Oct 24 i   i+- Re: Tonights Tradeoff - Background Execution Buffers1Robert Finch
12 Oct 24 i   i`- Re: Tonights Tradeoff - Background Execution Buffers1BGB
12 Oct 24 i   +* Re: Tonights Tradeoff - Carry and Overflow67Robert Finch
12 Oct 24 i   i`* Re: Tonights Tradeoff - Carry and Overflow66MitchAlsup1
12 Oct 24 i   i `* Re: Tonights Tradeoff - Carry and Overflow65BGB
12 Oct 24 i   i  `* Re: Tonights Tradeoff - Carry and Overflow64Robert Finch
13 Oct 24 i   i   +* Re: Tonights Tradeoff - Carry and Overflow3MitchAlsup1
13 Oct 24 i   i   i`* Re: Tonights Tradeoff - ATOM2Robert Finch
13 Oct 24 i   i   i `- Re: Tonights Tradeoff - ATOM1MitchAlsup1
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6 Nov 24 i   i    `* Re: Q+ Fibonacci57Robert Finch
17 Apr 25 i   i     `* Re: register sets56Robert Finch
17 Apr 25 i   i      +* Re: register sets53Stephen Fuld
17 Apr 25 i   i      i+- Re: register sets1Robert Finch
17 Apr 25 i   i      i+* Re: register sets46MitchAlsup1
18 Apr 25 i   i      ii`* Re: register sets45Robert Finch
18 Apr 25 i   i      ii `* Re: register sets44MitchAlsup1
20 Apr 25 i   i      ii  `* Re: register sets43Robert Finch
21 Apr 25 i   i      ii   `* Re: auto predicating branches42Robert Finch
21 Apr 25 i   i      ii    `* Re: auto predicating branches41Anton Ertl
21 Apr 25 i   i      ii     +- Is an instruction on the critical path? (was: auto predicating branches)1Anton Ertl
21 Apr 25 i   i      ii     `* Re: auto predicating branches39MitchAlsup1
22 Apr 25 i   i      ii      `* Re: auto predicating branches38Anton Ertl
22 Apr 25 i   i      ii       +- Re: auto predicating branches1MitchAlsup1
22 Apr 25 i   i      ii       `* Re: auto predicating branches36Anton Ertl
22 Apr 25 i   i      ii        `* Re: auto predicating branches35MitchAlsup1
23 Apr 25 i   i      ii         +* Re: auto predicating branches3Stefan Monnier
23 Apr 25 i   i      ii         i`* Re: auto predicating branches2Anton Ertl
25 Apr 25 i   i      ii         i `- Re: auto predicating branches1MitchAlsup1
23 Apr 25 i   i      ii         `* Re: auto predicating branches31Anton Ertl
23 Apr 25 i   i      ii          `* Re: auto predicating branches30MitchAlsup1
24 Apr 25 i   i      ii           `* Re: asynch register rename29Robert Finch
27 Apr 25 i   i      ii            `* Re: fractional PCs28Robert Finch
27 Apr 25 i   i      ii             `* Re: fractional PCs27MitchAlsup1
28 Apr 25 i   i      ii              `* Re: fractional PCs26Robert Finch
28 Apr 25 i   i      ii               +* Re: fractional PCs15MitchAlsup1
29 Apr 25 i   i      ii               i`* Re: fractional PCs14Robert Finch
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5 May 25 i   i      ii               i  `* Re: control co-processor12Al Kossow
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6 May 25 i   i      ii               i    +* Re: control co-processor3MitchAlsup1
7 May 25 i   i      ii               i    i+- Re: control co-processor1MitchAlsup1
15 Jul 25 i   i      ii               i    i`- Re: control co-processor1MitchAlsup1
7 May 25 i   i      ii               i    `* Scan chains (was: control co-processor)7Stefan Monnier
7 May 25 i   i      ii               i     +* Re: Scan chains (was: control co-processor)2Al Kossow
7 May 25 i   i      ii               i     i`- Re: Scan chains1Stefan Monnier
7 May 25 i   i      ii               i     +* Re: Scan chains3MitchAlsup1
7 May 25 i   i      ii               i     i`* Re: Scan chains2Stefan Monnier
8 May 25 i   i      ii               i     i `- Re: Scan chains1MitchAlsup1
15 Jul 25 i   i      ii               i     `- Re: Scan chains1MitchAlsup1
29 Apr 25 i   i      ii               `* Re: fractional PCs10Robert Finch
29 Apr 25 i   i      ii                `* Re: fractional PCs9MitchAlsup1
30 Apr 25 i   i      ii                 `* Re: fractional PCs8Robert Finch
30 Apr 25 i   i      ii                  +* Re: fractional PCs6Thomas Koenig
1 May 25 i   i      ii                  i+- Re: fractional PCs1Robert Finch
2 May 25 i   i      ii                  i`* Re: fractional PCs4moi
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2 May 25 i   i      ii                  i `- Re: fractional PCs1moi
30 Apr 25 i   i      ii                  `- Re: fractional PCs1MitchAlsup1
15 Jul 25 i   i      i`* Re: register sets5John Savard
15 Jul 25 i   i      i `* Re: register sets4MitchAlsup1
19 Jul 25 i   i      i  `* Re: register sets3Robert Finch
19 Jul 25 i   i      i   `* Re: register sets2Anton Ertl
19 Jul 25 i   i      i    `- Re: register sets1MitchAlsup1
15 Jul 25 i   i      `* Re: register sets2John Savard
15 Jul 25 i   i       `- Re: register sets1MitchAlsup1
13 Oct 24 i   `- Re: Tonights Tradeoff - Background Execution Buffers1Anton Ertl
4 Oct 24 +- Re: Tonights Tradeoff - Background Execution Buffers1BGB
6 Oct 24 `- Re: Tonights Tradeoff - Background Execution Buffers1MitchAlsup1

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