Re: control co-processor

Decided to create a co-processor for debugging and control of the main CPU. The co-processor takes up <2% of the design. It uses a subset of the same ISA but executes sequentially, taking five clocks per instruction.
It can in theory:
1) flush the main CPU's pipeline
2) inject a cache line into the pipeline (instructions + constants)
3) request a mapping of architectural to physical register
4) read/write a physical register value
5) stall the CPU pipeline
6) trigger single step mode
Also
Dump the trace buffer.
It has its own monitor program. Interface is with a serial port.
The CPU books I have do not cover a test/debug interface for the processor, so I am winging it a bit.
I figure with the ability to inject instructions just about anything could be accomplished albeit slowly.