Re: Tonight's tradeoff

Robert Finch wrote:

On 2024-03-07 1:39 a.m., BGB wrote:

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Bigfoot uses a whole byte for access rights, with separate read-write-execute for user and supervisor, and write protect for hypervisor and machine modes. He also uses 4 bits for the cache-ability which match the cache-ability bits on the bus.

Can you think of an example where a user Read-Only page would not be
writeable from super ?? Or a device on PCIe ??
Can you think of an example where a user Execute-Only page would not
be readable from super ?? Or a device on PCIe ??
Can you think of an example where a user page marked RWE = 000 would
not be readable and writeable from super ? Or a device on PCIe ??
Can you think of an example where 2-bits denoting {L1, L2, LLC, DRAM}
does not describe the cache placement of a line adequately ??

I am using the value of zero for the ASID to represent the machine mode’s ASID. A lot of hardware is initialized to zero at reset, so it’s automatically the machine mode’s. Other than zero the ASID could be anything assigned by the OS.

I do not rely on control registers being set to zero, instead part of
HW context switching end up reading these out of ROM and into those
registers--so they can have any reasonable bit pattern SW desires.
{{This is sort of like how Alpha comes out of reset and streams a ROM
through the scan path to initialize the internals.}}
I am also assuming that ASID = 0 is the highest level of privilege;
but this is purely a SW choice.