Re: Tonight's tradeoff

Scott Lurndal wrote:

mitchalsup@aol.com (MitchAlsup1) writes:

Scott Lurndal wrote:
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Robert Finch <robfi680@gmail.com> writes:

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Do they support using the entire page as a page table?

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All multilevel page tables use an entire page (granule in ARMv8)
at each level of the page table.    To map larger page/block sizes,
they just stop the table walk at one, two or three levels rather
than walking all four levels to the leaf page size.

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My 66000 page structure supports both skipping of levels in the table
and stopping at any level in the table.

That's all well and good.    What operating system do you
have running on the MY 66000 processor?   When will I be able
to purchase a system based on that processor?

Linux.

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Compression could be useful for something serialized to disk or through the network. Transferring the page number and compressed contents.

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Compressing tiered DRAM is looking to be the next big thing.

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 https://www.zeropoint-tech.com/news/meta-and-google-unveil-a-revolutionary-hardware-compressed-cxl-memory-tier-specification

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CXL is just* an offload of DRAM from an on-die memory controller to
an on-PCIe 5.0-6.0 high speed links.

Yes, I'm well aware of that.  What you don't mention is that it
can become part of the processor cache coherency domain.

My 66000 considers DRAM as part of the cache/memory hierarchy and
considers LLC as the front end to DRAM.

An interesting topic between PCIE 5.0 and 6.0 is the change from NRZ encoding to PAM 4. This comes with a degradation of error rate
from 10^-12 goes down to 10^-6, so you are going to need some kind
of ECC on the PCIe links and layers.

PAM4 is something with which we have a great deal of expertise,
along with the associated error correction.

I only point this out because it is "different".