Re: Efficiency of in-order vs. OoO

"Paul A. Clayton" <paaronclayton@gmail.com> writes:

On 3/24/24 4:39 PM, Scott Lurndal wrote:

mitchalsup@aol.com (MitchAlsup1) writes:

Paul A. Clayton wrote:

 

(I was also very surprised by how much extra state the A55 has:
over 100 extra "registers". Even though these are not all 64-bit
data storage units, this was still a surprising amount of extra
state for a core targeting area efficiency. The storage itself may
not be particularly expensive, but it gives some insight into how
complex even a "simple" implementation can be.)

...

However, having over 100 seems like a lot. Supporting performance
counters and tracing is also something that would have been nearly
inconceivable for something like the MIPS R2000.

Certainly.  The A55 is similar to the 21164 (1994), which is much
bigger than the R2000.  For competition to the R2000, better look at
the ARM1/ARM2, or, for something more contemporary, maybe the
Cortex-M1.

An argument might be made that some designs would have no use for
most of such extra state. Performance monitoring is useful for
software development (and theoretically for OS decisions for
scheduling, core migration, and other functions), but seems likely
to be highly underutilized for typical use. A55 is presumably
large enough that a synthesis-time remove of much of this
functionality would have a tiny effect on total area.

ARM also has the Cortex-A35 (with a 25% smaller core than the A53 and
80-100% of its performance according to ARM).  I am unaware of it
being used in smartphones, though.

Even for a
microcontroller the area cost might not be problematic.

ARM-A is not for microcontrollers.  ARM has ARM-M for that, e.g., the
Cortex-M0 if you want it to be really small.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>