Re: Efficiency of in-order vs. OoO

Scott Lurndal wrote:

"Paul A. Clayton" <paaronclayton@gmail.com> writes:

On 3/24/24 4:39 PM, Scott Lurndal wrote:

There is a significant demand for performance monitoring.   Note
that in addition to to standard performance monitoring registers,
AArch64 also (optionally) supports statistical profiling and
out-of-band instruction tracing (ETF).   The demand from users
is such that all those features are present in most designs.

My 66000 Architecture defines 8 performance counters at each layer of the design:: cores gets 8 counters, L1s gets 8 counters, L3s gets 8 counters Interconnect gets 8 counters, Memory Controller gets 8 counters, PCIe root gets 8 counters--and every instance multiplies the counters. All counters are available via MMI/O space, and can be copied out or reinitialized in a single LDM, STM, or MM instruction. Any thread with
a TLB mapping can read or write based on permission bits.