Re: Another security vulnerability

scott@slp53.sl.home (Scott Lurndal) writes:

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:

scott@slp53.sl.home (Scott Lurndal) writes:

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:

Also, if the prefetcher works with data in a shared cache (I don't
know whether the data-dependent prefetchers do that), it may not
matter on which core the code runs.

>
Run it in non-cacheable memory.  Slow but safe.

>
To eliminate this particular vulnerability, it's sufficient to disable
the data-dependent prefetcher.

>
That assumes that chicken bit(s) are available to do that.

The hardware designers have put in the chicken bit(s); it's highly
unlikely that they have unconditionally enabled the data-dependent
prefetcher on M1 and M2, and only added a chicken bit on M3.  Now that
the hardware indeed turns out to be broken, they just need to activate
it/them.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>