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On 4/11/2024 6:13 AM, Michael S wrote:On Wed, 10 Apr 2024 23:30:02 +0000
mitchalsup@aol.com (MitchAlsup1) wrote:
It does occupy some icache space, however; have you boosted the>
icache size to compensate?
The space occupied in the ICache is freed up from being in the
DCache so the overall hit rate goes up !! At typical sizes,
ICache miss rate is about ¼ the miss rate of DCache.
>
Besides:: if you had to LD the constant from memory, you use a LD
instruction and 1 or 2 words in DCache, while consuming a GPR. So,
overall, it takes fewer cycles, fewer GPRs, and fewer
instructions.
>
Alternatively:: if you paste constants together (LUI, AUPIC) you
have no direct route to either 64-bit constants or 64-bit address
spaces.
>
It looks to be a win-win !!
Win-win under constraints of Load-Store Arch. Otherwise, it
depends.
Never seen a LD-OP architecture where the inbound memory can be in
the Rs1 position of the instruction.
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