Re: "Mini" tags to reduce the number of op codes

Michael S <already5chosen@yahoo.com> writes:

On Thu, 11 Apr 2024 18:46:54 +0000
mitchalsup@aol.com (MitchAlsup1) wrote: 

 

It looks to be a win-win !! =20 

=20
Win-win under constraints of Load-Store Arch. Otherwise, it
depends. =20 

=20
Never seen a LD-OP architecture where the inbound memory can be in
the Rs1 position of the instruction.
=20 

>
May be. But out of 6 major integer OPs it matters only for SUB.
By now I don't remember for sure, but I think that I had seen LD-OP
architecture that had SUBR instruction. May be, TI TMS320C30? 

 
ARM has LDADD - negate one argument and it becomes a subtract.