Re: "Mini" tags to reduce the number of op codes

On 4/9/24 13:24, Thomas Koenig wrote:

I wrote:
 

MitchAlsup1 <mitchalsup@aol.com> schrieb:

Thomas Koenig wrote:
>

John Savard <quadibloc@servername.invalid> schrieb:

>

Thus, instead of having mode bits, one _could_ do the following:
>
Usually, have 28 bit instructions that are shorter because there's
only one opcode for each floating and integer operation. The first
four bits in a block give the lengths of data to be used.
>
But have one value for the first four bits in a block that indicates
36-bit instructions instead, which do include type information, so
that very occasional instructions for rarely-used types can be mixed
in which don't fill a whole block.
>
While that's a theoretical possibility, I don't view it as being
worthwhile in practice.

>

I played around a bit with another scheme:  Encoding things into
128-bit blocks, with either 21-bit or 42-bit or longer instructions
(or a block header with six bits, and 20 or 40 bits for each
instruction).

>
Not having seen said encoding scheme:: I suspect you used the Rd=Rs1
destructive operand model for the 21-bit encodings. Yes :: no ??

>
It was not very well developed, I gave it up when I saw there wasn't
much to gain.

 Maybe one more thing: In order to justify the more complex encoding,
I was going for 64 registers, and that didn't work out too well
(missing bits).
 Having learned about M-Core in the meantime, pure 32-register,
21-bit instruction ISA might actually work better.

If you want to know more about MCore, you can contact me.
I was the initial designer of the mcore ISA.  It was targeted
at embedded processors, particularly control processors in phones
and radios.  It was extended and found its way into GPS receivers and
set top boxes.  Motorola licensed it to the Chinese and there it is
known as CSky ISAv1 (there is a different ISAv2).  There is even a
supported Linux port of CSky v1.
brian