Stealing a Great Idea from the 6600

Not that I expect Mitch Alsup to approve!

The 6600 had several I/O processors with a 12-bit word length that
were really one processor, basicallty using SMT.

Well, if I have a processor with an ISA that involves register banks
of 32 registers each... an alternate instruction set involving
register banks of 8 registers each would let me allocate either one
compute thread or four threads with the I/O processor instruction set.

And what would the I/O processor instruction set look like?

Think of the PDP-11 or the 9900 but give more impiortance to
floating-point. So I've come up with this format for a part of the
instruction set:

0 : 1 bit
(First two bits of opcode: 00, 01, or 10 but not 11): 2 bits
(remainder of opcode): 5 bits
(mode, not 11): 2 bits
(destination register): 3 bits
(source register): 3 bits

is the format of register-to-register instructions;

but memory-to-register instructions are load-store:

0: 1 bit
(first two bits of opcode: 00, 01, or 10 but not 11): 2 bits
(remainder of load/store opcode): 3 bits
(base register): 2 bits
(mode: 11): 2 bits
(destination register): 3 bits
(index register): 3 bits

(displacement): 16 bits

If the index register is zero, the instruction refers to memory, but
is not indexed, as usual.

An almost complete instruction set, using 3/8 of the available opcode
space. Subroutine call and branch instructions, of course, are still
also needed.

John Savard