Re: 208 B transistors !!

EricP wrote:

MitchAlsup1 wrote:

EricP wrote:
 

MitchAlsup1 wrote:

https://youtube.com/shorts/x5aiu7BTi7E?si=0knTN4-yUVOXSEsy

 

A quicky search finds the current EUV maximum reticle size is
about 26 mm by 33 mm or 858 mm² (~1 inch by 1.25 inch).

 

That chip sure looks bigger than that.

 It looks to me about 4× that reticle limit.
 In the early 1980s someone (Amdahl?) was working on wafer scale
lithography, apparently we have now arrived.....

As part of a sales deal, in 1981 my then employer rented me and
another guy for on-site support to Trilogy Systems,
Amdahl's then attempt to build wafer scale IBM 370 compatibles.
I got to live in sunny Palo Alto all expense paid for 6 months.

I really enjoyed my time in "the valley" for the 18 months I was there.
All expenses paid would have been a goodly bonus situation.

Trilogy were building it with ECL macro cells on 3" wafers
with interconnect wires patterned between 0.25" * 0.25" reticles,
trimmed down to a single chip about 2.5" by 2.5" afterwards.

Part of it was inventing a way to dissipate 1200 watts from
the above chips, using liquid freon IIRC.

Imagine how quickly a 1 oz hunk of silicon would get hot at 1200 Watts
of input power.

Also there was no software CAD tools then so all that had to be
invented from scratch too.

They burned through $250 million in seed capital (DEC was one investor)
and closed, merged into Elxsi according to Wikipedia.

There have been similarly large expenditures in AI chips over the last
decade.....to mostly naught.