Short Vectors Versus Long Vectors

Adding the typical kind of vector-processing instructions to an
instruction set inevitably leads to a combinatorial explosion in the
number of opcodes. This kind of thing makes a mockery of the “R” in
“RISC”.

Interesting to see that the RISC-V folks are staying off this path;
instead, they are reviving an old idea from Seymour Cray’s original
machines that bear his name: a vector pipeline. Instead of being limited
to processing 4 or 8 operands at a time, the Cray machines could operate
(sequentially, but rapidly) on variable-length vectors of up to 64
elements with a single setup sequence. RISC-V seems to make the limit on
vector length an implementation choice, with a value of 32 being mentioned
in the spec.

The way it avoids having separate instructions for each combination of
operand types is to have operand-type registers as part of the vector
unit. This way, only a small number of instructions is required to set up
all the combinations of operand/result types. You then give it a kick in
the guts and off it goes.

Detailed spec here:
<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc>.