Re: Stealing a Great Idea from the 6600

On 4/23/2024 1:54 AM, John Savard wrote:

On Mon, 22 Apr 2024 20:22:12 -0600, John Savard
<quadibloc@servername.invalid> wrote:
 

But fully half the opcode space is allocated to 16-bit instructions.
EVen though that half doesn't really play nice with other things, it's
too tempting a target to ignore. But the price would be losing the
fully parallel nature of decoding.

 After heading out to buy groceries, my head cleared enough to discard
the various complicated and bizarre schemes I was considering to deal
with the issue, and instead to drastically reduce the overhead for the
instructions longer than 32 bits, now that this had become a major
concern due to also usiing this format for prefixed instructions as
well, in a simple and straightforward manner.
 

You know, one could just be like, say:
                       xxxx-xxxx-xxxx-xxx0  //16-bit op
   xxxx-xxxx-xxxx-xxxx xxxx-xxxx-xxxx-xx01  //32-bit op
   xxxx-xxxx-xxxx-xxxx xxxx-xxxx-xxxx-x011  //32-bit op
   xxxx-xxxx-xxxx-xxxx xxxx-xxxx-xxxx-0111  //32-bit op
   xxxx-xxxx-xxxx-xxxx xxxx-xxxx-xxxx-1111  //jumbo prefix (64+)
And call it "good enough"...
Then, say (6b registers):
                       zzzz-mmmm-nnnn-zzz0  //16-bit op (2R)
   zzzz-tttt-ttss-ssss nnnn-nnpp-zzzz-xxx1  //32-bit op (3R)
   iiii-iiii-iiss-ssss nnnn-nnpp-zzzz-xxx1  //32-bit op (3RI, Imm10)
   iiii-iiii-iiii-iiii nnnn-nnpp-zzzz-xxx1  //32-bit op (2RI, Imm16)
   iiii-iiii-iiii-iiii iiii-iipp-zzzz-xxx1  //32-bit op (Branch)
Or (5b registers):
                       zzzz-mmmm-nnnn-zzz0  //16-bit op (2R)
   zzzz-zttt-ttzs-ssss nnnn-nzpp-zzzz-xxx1  //32-bit op (3R)
   iiii-iiii-iiis-ssss nnnn-nzpp-zzzz-xxx1  //32-bit op (3RI, Imm11)
   iiii-iiii-iiii-iiii nnnn-nzpp-zzzz-xxx1  //32-bit op (2RI, Imm16)
   iiii-iiii-iiii-iiii iiii-iipp-zzzz-xxx1  //32-bit op (Branch)
...

John Savard