Re: Short Vectors Versus Long Vectors

Lawrence D'Oliveiro <ldo@nz.invalid> writes:

On Tue, 23 Apr 2024 19:25:22 -0600, John Savard wrote:
Looking at an old Cray-1 manual, it mentions, among other things, sixty
four 64-bit intermediate scalar “T” registers, and eight 64-element vector
“V” registers of 64 bits per element. That’s a lot of registers.
>
RISC-V has nothing like this, as far as I can tell. Right at the top of
the spec I linked earlier, it says:
>
   The vector extension adds 32 architectural vector registers,
   v0-v31 to the base scalar RISC-V ISA.
>
   Each vector register has a fixed VLEN bits of state.
>
So, no “big vector registers” that I can see? It says that VLEN must be a
power of two no bigger than 2**16, which does sound like a lot, but then
the example they give only has VLEN = 128.

It's an example.  If you think you can make and profitably sell a CPU
with VLEN=4096 (the number of bits in one of Cray-1's vector
registers), that would be compliant with the spec, and would run
programs written for RISC-V with the vector extension.  Or you can
make one with VLEN=65536 and claim that you have the longest one:-).

This leaves you free to decide VLEN based on the costs and benefits in
the context of the other design decisions you have made and on the
programs you expect to run.

Note that the Fujitsu A64FX (which implements the similar ARM Scalable
Vector Extension and was designed for supercomputing) chooses a
512-bit vector implementation.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>