Re: Short Vectors Versus Long Vectors

Anton Ertl wrote:

John Savard <quadibloc@servername.invalid> writes:

And if memory bandwidth issues make Cray-style vector machines
impractical, then wouldn't it be even worse for GPUs?

The claim by Mitch Alsup is that latency makes the Crays impractical,
because of chaining issues.  Do GPUs have chaining?  My understanding
is that GPUs deal with latency in the barrel processor way: use
another data-parallel thread while waiting for memory.  Tera also
pursued this idea, but the GPUs succeeded with it.

- anton

Consider:: an 8 deep CRAY-like vector calculation with 8 cycle latency
memory and 6 cycle latency FMAC::
     |LD|LD|LD|LD|LD|LD|LD|LD|
                             |FM|FM|FM|FM|FM|FM|FM|FM|
                                               |ST|ST|ST|ST|ST|ST|ST|ST|
Not much parallelism. Now consider the same machine above with longer vectors::
     |LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|
                             |FM|FM|FM|FM|FM|FM|FM|FM|FM|FM|FM|FM|FM|FM|FM|FM|
                                               |ST|ST|ST|ST|ST|ST|ST|ST|ST|ST|ST|ST|ST|ST|ST|ST|
Now we have considerable parallelism with no change in latencies.
Later consider the top execution profile augmented with a bit of OoO
and a second memory port::
     |LD|LD|LD|LD|LD|LD|LD|LD|
                             |FM|FM|FM|FM|FM|FM|FM|FM|
     |SA|SA|SA|SA|SA|SA|SA|SA|                 |Sd|Sd|Sd|Sd|Sd|Sd|Sd|Sd|
Finally consider a GBOoO implementation::
     |LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|LD|...
     |Fq|Fq|Fq|Fq|Fq|Fq|Fq|Fq|Fq|Fq|Fq|Fq|Fq|Fq|Fq|Fq|...
                             |FM|FM|FM|FM|FM|FM|FM|FM|...
     |SA|SA|SA|SA|SA|SA|SA|SA|SA|SA|SA|SA|SA|SA|SA|SA|...
                                               |Sd|Sd|Sd|Sd|Sd|Sd|Sd|Sd|...
Here it takes an execution window 18 deep to reach pipeline saturation,
but once you do, the core runs at 3 instructions and arguably 4 units
of work per cycle {without including loop overheads}. In order to
achieve such performance one needs to issue the whole loop in 1 cycle.
You have to have the requisite bandwidths {AGEN, bank access, address
routing bandwidth, result return bandwidth, FMAC bandwidth} but you
also have to have the requisite latencies (and excecution window width)
or it falls apart that enable the vector chaining to work.