Re: Oops (Concertina II Going Around in Circles)

On Thu, 25 Apr 2024 12:41:23 -0600, John Savard
<quadibloc@servername.invalid> wrote:

While I'm rearranging the deck chairs, maybe I'll come up with an
original idea.

This latest proposal, which does differ from my previous attempts,
does have _one_ advantage.

In this case, as in the previous attempts, I will need to use the
block header to indicate that some 32-bit instruction slots contain
32-bit instructions in an "alternate" format.

When the memory-reference instructions in the main format were
compromised, that alternate format included uncompromised
memory-reference instructions.  So the extended instruction set,
normal plus alternate, included the normal instructions twice.

Here, I avoid that. Of course, though, the main format includes a
severely compromised version of the register-to-register operate
instructions. The alternate format would include the full version of
those.

Same thing, right?

Well, not really - because the compromised version of
register-to-register operate instructions contains only *one*
instruction format. So there _is_ less duplication and waste, the
instruction decode unit isn't set up to decode both the full version
of the operate instructions and a second compromised format which is
equally complex, but just has one bit trimmed off everywhere.

John Savard