Re: Byte Addressability And Beyond

On Thu, 2 May 2024 01:18:59 -0000 (UTC), John Levine wrote:

It appears that Lawrence D'Oliveiro  <ldo@nz.invalid> said:

>

 "Unlike Swift's, the computer Endian controversy is not pointless.
 The Little Endian design has many complications in use; we much
 prefer the Big Endian."

>
It’s easy to illustrate why they’re wrong. First of all, a note that,
even on big-endian architectures, registers are still actually
little-endian.

 
I would be most interested in a concrete illustration of this
implausible argument.

Sure. Consider this pseudo-assembly-language sequence:

    move.l a, b
    move.b b, c

where “move” denotes either “load” or “store” as appropriate, the “.b”
suffix indicates a byte operation, and “.l” denotes a multibyte operation
(2, 4, 8 bytes or whatever, doesn’t matter as long as it’s more than 1).

As for the labels “a”, “b” and “c”, they can be reasonably interpreted (to
accommodate both RISC and non-RISC architectures) in two ways:
1) “a” and “c” are registers, “b” is a memory address; or
2) “b” is a register, while “a” and “c” are memory addresses.

Now the question is: which byte from “a” ends up at location “c”?

On a little-endian architecture, it is always the lowest-significance
byte.

But on a big-endian architecture, for a register-memory-register move, it
will be the highest-significance byte. But for the memory-register-memory
case, it will be the lowest-significance byte.

In other words, even on big-endian architectures, registers are still
interpreted as little-endian!

Isn’t that fun?