Re: 208 B transistors !!

On 5/2/2024 9:23 PM, MitchAlsup1 wrote:

BGB wrote:
 

>
I guess, if one could get it to run at MHz speeds, this could be enough for a CPU.

 

Though, would likely need multiple passes through the printer to print something like this, say:
   Print transistor layers;
   Bake the sheet;
   Print insulator and metal trace layers;
   Bake;
   Print more insulator and metal trace layers;
   Bake;
   ...

 A starting point::
 https://youtube.com/shorts/-eeazBcavUE?si=nGNykOGIrTsvGGL-

Yeah, the most likely ink that would be used for making the transistors (PEDOT:PSS) is apparently fairly commonly used for printed solar cells and OLED displays. One could in theory make solar cells and OLEDs using the same general process.
Though, it is not cheap. At the moment, "poking around at it" is not really enough to justify dropping around $1k mostly for an expensive inkjet and a bottle of PEDOT:PSS ink.
Did at least end up buying the parts to make the oven, but they are over at the machine-shop right now. This was the cheap part, but could also be used for solder reflow and powder coating, so is easier to justify.
Well, technically, the printable PET plastic is cheaper than the toaster oven was, but more expensive than a ream of printer paper (and around 10x the cost per sheet).
Well, there are also acrylic sheets (intended for overhead projectors), but PET has a higher melting point than PMMA. For the baking process, one wants a sheet that wont melt or deform, and can hopefully tolerate being soldered onto. The melting point for PMMA being lower than the melting point for 60/40 solder, but PET being higher.
Though, one would need a temperature-controlled iron, since if the soldering iron gets to hot, it would also melt PET, so would need to keep the iron below a limit of around 220 or 230C or so (melting point of PET being ~ 250C); though in my case, I had already bought a soldering station with this feature, and also a desoldering gun.
Well, also temperature control is useful for not causing the solder pads and traces to come off the PCB (say, if one exceeds 220C, then things like phenolic PCBs are not too happy either).
...
Some likely difficult issues would be things like getting the sheets loaded back into the printer with sufficiently accurate alignment between passes.
Like, say, if the sheet alignment was only accurate to around 0.030" or so, then this would have a significant adverse effect on possible transistor density (and the DPI of the printer would not matter so much in this case).
Though, the main likely source of variability here would be in the tray or paper-feed mechanism.
The place-and-route is also uncertain, but in theory is possible.
Would likely work by getting a Verilog compiler to spit out a netlist, probably telling Yosys to pretend it is targeting a Lattice ICE40 or ECP5 or similar.
Would likely need to manually design basic components like logic gates and flip-flops. Logic gates could be defined for every possible 2->1 truth-table.
Possible LUT2 gates:
   0000: Wired to GND
   0001: AND
   0010: -
   0011: Buffer (Ignore B)
   0100: -
   0101: Buffer (Ignore A)
   0110: XOR
   0111: OR
   1000: NOR
   1001: XNOR
   1010: Inverter (Ignore B
   1011: -
   1100: Inverter (Ignore A)
   1101: -
   1110: NAND
   1111: Wired to VSS
Where, for the '-' gates, would need to come up with something.
Here, 0010 and 0100 are A/B mirrors, as are 1011 and 1101 (and logically inverted from the former). This seems to be some sort of unnamed/unknown asymmetric logic gate (seemingly an AND or NAND gate with either A or B inverted).
Mental estimate is that all cases should be possible within 4 transistors and 3 resistors (and seemingly would need to decide between active-high and active-low logic, though AFAIK typically active-high is more common).
Could then procedurally generate every possible LUT3 and LUT4. Going beyond LUT4 would not be likely be plausible with this approach (LUT4 having 2^16 possible truth-tables, LUT5 and LUT6 having 2^32 and 2^64).
Seems like every possible LUT3 should be possible with 3 gates (2 gates deep), and every possible LUT4 with 7 gates (3 gates deep). Though, it is likely that many truth tables could be done in less.
A LUT5 would need 15 gates and LUT6 31 gates, they could be possible if they were generated "on the fly" rather than trying to prebuild and store gates for every possible truth table.
Though, less obvious how to approach LUTRAM (Distributed RAM) and SRAM blocks. Might make sense to somehow tell synthesis that the device lacks any SRAM type blocks, and to use FF's for everything
I am guessing, a LUTRAM cell would likely need to contain some MUX logic and a collection of flip-flops, and so probably significantly larger than a bare LUT or FF.
( Though, admittedly, trying to imagine the structure of a LUTRAM cell is pushing the limits of my visual imagination, and most of what my imagination is coming up with seems comparably very large... ).
For resistors, most likely option seems to be to make a transistor with a fairly narrow channel, and then to hard-wire it in the ON state (say, Gate is wired to Drain or similar).
Internally, could probably represent the logic layers as 16-color BMP images or similar (likely LZ compresssed to save space, and representing CMY rather than RGB).
Though, technically probably only need 2 bits/pixel in this case, say:
   00: Nothing
   01: Insulator
   10: Metal
   11: PEDOT
Though, would likely need to design the transistors and logic gates in a graphics editor (probably Paint.NET or similar), with a logical mapping from pixel color to material.
Say:
   White: Nothing
   Green: Insulator
   Red: Metal
   Blue: PEDOT
But, not sure if there is a convention for this.
Final output would likely need to be TIFF or something (for hopefully direct CMYK control of the printer). Or, maybe try expressing the colors in RGB (but matched to an inverse CMYK transform), and then hope the printer doesn't mix the inks too much.
Then again, nothing is to say that the graphics programs and printer wouldn't go CMYK -> RGB -> CMYK, rendering the use of TIFF effectively moot in this case (in which case, may as well just use PNG or TGA or similar).
...