Re: a bit of history, Stealing a Great Idea from the 6600

Anton Ertl wrote:

John Levine <johnl@taugh.com> writes:
[only 2 condition code bits]

In their archtecture book Brooks and Blaauw say it was a mistake, but
it also would have been a problem to fit conditional branches into the
instruction set if they needed more instruction bits to say which
codes to test. As it was, the branch instructions had 4 condition bits
which let them check for any combination of two-bit conditions along
with 1111 for unconditional branch and 0000 for no-op.

The architecture paid for the reduction in branches with an increase
in other instructions; S/360 needed signed and unsigned versions of a
number of instructions, e.g.,

signed unsigned
A      AL
AR     ALR
S      SL
SR     SLR
C      CL
CR     CLR

Other instruction sets with 16-bit instructions have no problem
supporting the usual NCZV flags.

IBM then continued in their tradition by having < = > and sticky
overflow flags in Power (and a separate carry, sticky overflow and
overflow flag); this also requires signed and unsigned compares (cmp
and cmpl along with variants).

All of which are constraining to the compiler:: for example::
     if( x >= y )
         then-clause
     else
         else-clause     // NANs go here
Cannot be clause reversed into::
     if( x < y )
         else-clause
     else
         then-clause     // NaNs go here
But also consider an architecture without any condition codes makes these
transformations easy::
     if( !( x >= y ) )
         else-clause      // NaNs go here
     else
         then-clause
The transformation is easy because the result of a compare instruction
is a bit vector; one bit corresponds to >=, another corresponds to !>=;
fixing a problem that condition code machines find difficult.
And yet even here, there is no signed compare and no unsigned compare;
there is just a compare that performs signed and unsigned, then-else
and else-then, and a few more.

- anton