Re: a bit of history, Stealing a Great Idea from the 6600

Thomas Koenig wrote:

MitchAlsup1 <mitchalsup@aol.com> schrieb:

(*) x86 takes craploads of cycles to cross the trap barrier and back
{including the saving and restoration of registers}
Something like My 66000 takes 10 each way including the saving and restoring of registers, and the change of MMU state.

(Maybe) stupid question: What happens to in-flight instructions on
such a trap, or an interrupt?  What is the cost of that?

All instructions before the trap/exception/interrupt are allowed to complete
No  instructions beyond the trap/exception/interrupt are allowed to complete
Those instructions still in flight are allowed to proceed while the state
and register file of the handler are fetched from memory. If they complete
before state arrives, the overhead is zero. If they are still pending, then
latency accrues from that point.