Re: Byte Addressability And Beyond

EricP wrote:

MitchAlsup1 wrote:

BGB wrote:
 

On 5/5/2024 10:31 AM, Scott Lurndal wrote:

Thomas Koenig <tkoenig@netcologne.de> writes:

Scott Lurndal <scott@slp53.sl.home> schrieb:
>

 

Not as of yet in my case, but bitfield extract might happen eventually.
Issue is finding a way to pull it off that is useful and cheaper than shift+mask (and probably adding some mechanism to pattern-match it from the AST or similar).

 But, but but but:: it IS shift and Mask !!
 

Annoyingly, a good general case instruction could not be encoded in a 32-bit instruction form at this point (could either add a few special cases as 32-bit ops, or use a 64-bit encoding; or do it as a 2RI op rather than 3RI but this is lame...).

 

Then again, say:
   BITEXTR  Imm10, Rn  //Rn=(Rn>>(Imm&63))&((1<<((Imm>>6)&15))-1)
Could potentially still be useful.

     SL    Rd,Rc,<width:offset>
 Is a bit field extract instruction, it is also a smash instruction (smashing a 64-bit value into a 8-bit or 12-bit or 47 bit for whatever
purpose is needed)
     SR    Rd,Rc,<width:offset>
 Positions the value in a register (Rc) such that it fits the alignment of
a field.
     INS   Rd,Rc,Rf,<width:offset>
 Inserts the field from Rf into its position <w:o> in Rc, inserts the field and delivers the new container to Rd.

I think my instruction set could accomplish pretty much the same
efficiency for bit field operations as bit addresses but without
requiring direct bit addressing.

An issue that comes up is when the in-memory bit field is > 56 bits wide
as it might straddle two 64-bit words. If width is <= 56 bits then
a load from a byte address handles most of the shifting and the
rest can be handled within a single register.

This is what CARRY is for--access to 128-bit in 2×64-bit out shifts.
CARRY can be used for extracts and for inserts.

But if the in-memory bit field is > 56 bits wide it may or may not straddle
a single 64-bit memory location, and require a pair of registers to loaded.

I don't understand 56--56 takes just as many bits to encode as 63 ?!?

I added an optional second dest register field to my ISA to allow operations
like wide bit field extract and insert across a pair of registers.
Also for wide arithmetic.

I was thinking of variable length LDV and STV load & store instructions
to work with variable length byte fields from 1 to 16 bytes.

32 gives you access to an arithmetic space where you can calculate
world GDP in the least valuable currency world-wide not lose a cent
on the bottom end and not overflow on the top by 20-odd bits.

LDV has two dst registers, a normal byte address specifier,
and a byte count from 1 to 16 to load. All high order bytes
not written by the LDV are zero filled.
The byte count can be an immediate or in a register.

STV does the same for stores with a pair of source value registers.

LDV and STV only touch the memory bytes they actually load or store.
So if the actual address + byte count does not touch a second 64-bit
memory word then they don't touch the next cache line or next page
in the case of potential page straddles.

This allows code to LDV up to 16 bytes into a register pair
extract and insert up to 64-bit fields in that register pair,
then STV only the bytes operated on,
with HW taking care of the special cases of straddle/not-straddle.