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On Mon, 06 May 2024 11:06:44 -0600, John Savard
<quadibloc@servername.invalid> wrote:
>But because that code conflicts with the header, these things aren't>
first-class citizens! I tried freeing up 1110 as well, but that was
clearly not going to work acceptably. So I took other measures that
only partly addressed that issue but consumed far less opcode space.
Although I had limited long vector and short vector operate
instructions in the basic 32 bit instruction set, I didn't have long
vector and short vector load and store instructions of any kind. Do I
needed to add them in some form in order for the basic 32 bit
instruction set to be complete.
>
However, if I were to include a 6-bit length field in the long vector
load and store instructions, once again I would have had to free up
1/16 of the opcode space. Instead of completely doing without the
ability to load and store any but full-length vectors, I eventually
was able to include a two-bit length register field to the long vector
load and store instructions.
>
So this new instruction set has survived another challenge.
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