Re: why bits, Byte Addressability And Beyond

I wanted to hint that in typical situation, i.e. when one 32-bit or
64-bit load serves several bit field extractions, his additional
instruction would be slower rather than faster than existing practice.

The way I imagine bit-addressability, it would basically work as
follows:

- Use pointers almost as we do now, except shifted by 3 bits.
  Most likely normal loads and stores would signal an error if the low
  3 bits aren't 0.  Immediate offsets in instructions would presumably
  still be in the same units as before (bytes, words, ...).

This is fundamentally the only thing needed.
But once you have that, you'd probably want to add some instructions to
each bit-granular processing, which I'd imagine would look like:

- Load/store operations that ignore the lowest 3 bits (or
  more than that, maybe the lowest 6 bits).
- bit-insertion/extraction instructions which use those lowest 3-6bits
  and ignore the rest.

This would not require any special shifter in the memory path and the
combination of those operations should be just as efficient as
a dedicated instruction.

To handle bitfields that straddle word boundaries, you might want
your bit-insert/extract to come with a "double-wide" option (I guess My
66000's CARRY could do the trick), tho maybe you'd just use something
like a 64bit load/store which only ignores the lowest 5bits (should be
sufficient for any bit-field up to 32bits).


        Stefan