Re: Oops (Concertina II Going Around in Circles)

John Savard wrote:

On Wed, 8 May 2024 21:46:37 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:

So, why do you need a header AT ALL !!

Assuming I don't want to ever allow the circuits of my computer to try
decoding an instruction that turns out later to be data (unless the
programmer has made an error, in which case the penalty of the program
being aborted is no problem)...

and I want the computer to be able to decode all the instructions in a
block in parallel, as a way to improve performance,

What makes you think My 66000 ISA cannot be decoded in parallel ??
Over the last year I have illustrated how up to 16 instructions,
each variable length from 1..5 words, can be decoded in parallel.
First you select a suitable buffer which presents instructions to be
decoded. A 6-wide machine will be using 16 words.
Each word (320-gates of flip flops) has a 40-gate size decoder,
and this size is used to select its successor.
The first instruction starts at IP, the next is selected from the
decode of the first instructions (4 gates of delay). Here after,
the selection of the second instruction selects instructions 3 and
4. Next we select instructions 5 through 8, then 9 through 16.
8 total gates of logic and several gates of fan-out buffering.
I happen to call this parse--instructions are parsed into individual
starting points. and up to 16 instructions are presented to 16
instruction decoders. Each of these decoders decodes the entire ISA.
{Although there are ways to route instructions to more specialized
decoders if desired.}}
You are using a header, I am using logic.
By using logic, there is no waste of bits in the instruction encoding.

then I need a block header to say 'here are the instructions to
decode' IF I don't want to be absolutely limited to all instructions
having the same length.

Seems like a horrible plan going forward with your goals in mind.

While I could still have a pair of 16-bit instructions in a 32-bit
word, without headers I couldn't have immediates (at least not of most
lengths), or other instructions longer than 32 bits.

And headers let me add instruction predication, which is also good, as
branches do cause difficulties which predication partly avoids.
(There's still a dependency on what is being predicated upon.)

I added predication without any such need.

The header facilitates fast decoding of a flexible instruction set,
and allows VLIW features allowing the ISA to be used for embedded
processors.

The header allows subtracting 1 stage from the 12+ stage k-wide pipeline,
AND is causing all sorts of "other issues" to remain present.

John Savard