Re: Oops (Concertina II Going Around in Circles)

On Wed, 8 May 2024 21:46:37 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:

John Savard wrote:

But what if the new feature was so important that I needed to have
*short* instructions for the operations using that feature - 32-bit
long instructions?

G A S P ........why do I even try.....

I'm not sure why what I said _there_ was so shocking.

But, yes, I do freely admit that Concertina II is _not_ an ISA that
"makes sense" from your point of view... or, indeed, the point of view
of many other people who value simplicity and elegance in a computer
architecture.

Instead, right from the start, it gives the appearance of having
accumulated the kind of cruft that usually is acquired though decades
of maintaining backwards compatibility.

Still, I know that what I'm leading up to is shocking.

The ISA looks - at first glance - like a plain old 32-bit RISC
architecture. With a few little peculiarities... base-index
addressing, like the 360, but not like any RISC architecture, for
example.

And then people notice the headers.

Code is divided into 256-bit blocks, so that instructions can have
"pseudo-immediates"; these values can be stacked at the end of a block
so that they're all aligned, and they don't cause the instructions
themselves to vary in length, so decoding is simple.

Could that be regarded as tolerable?

And the headers also allow... explicit indication of when instructions
can execute in parallel, and instruction predication. Oh, so it's
VLIW, too?

And then they notice the killer. Perhaps they, too, will "gasp" in
shock.

There's also a header type that allows code where 16, 32, 48, 64...
bit instructions can be combined in any order, for tracitional
CISC-like code with a variable instruction size. But there's a 12.5%
overhead penalty so that fast parallel  decoding remains available.

But that header does something else.

It changes the instruction stream from being composed of 32-bit words
to one composed of 36-bit words, divided into 18-bit halfwords.

And if that isn't enough, the last two header types let you switch to
38-bit words composed of two 19-bit halfwords. *That's* what I do to
add a bunch of extra 32-bit instructions to the ISA, if some new
feature is so important that I don't want the instructions that deal
with it to have to be 48 bits long at least.

And, yes, I can indeed understand why you might gasp in horror at that
stage. But you said I was having problems running out of opcode space,
so I had to demonstrate that I could pull new opcode space out of thin
air, as it were, should I feel the need to do so.

John Savard