Re: Oops (Concertina II Going Around in Circles)

John Savard wrote:

On Fri, 10 May 2024 17:27:10 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:

Or skip to the end and only invent AVX while skipping the soon-to-be
redundant intermediate stages.

Well, I went to 256-bit short vectors as a permanent part of the
architecture, with long vectors as the next step.

But what about crypto assist instructions, as another example?

If used often enough, sure, they make a lot of sense--just make whatever
you put in applicable to a myriad of crypto functions.

However, I think I will adjust this feature. You comlained I used up
too much of my opcode space, so I demonstrated that Concertina II had
the potential to have... a _lot_ of opcode space, even to ludicrous
lengths.

Now that I think I can finally wrap up Concertina II, having found how
to achieve its goals as best as possible, I can go on to Concertina
III... and, given your anguished pleas, I _will_ give up on block
structure for the next iteration.

Would you like to read My 66000 ISA while taking a break between CT II and
CT III ??

In order to do that, though, it will have to be CISC, not RISC...
banks of 8 registes, sort of like Concertina I, but much less messy.

With MEM-OPs are you not already CISC ??
Plu8s, not only is CISC<->RISC not a proper metric but merely points
along a complexity spectrum--one the RISC camp has used to oversell
their case.
My point is that there is a point between CISC and RISC where it takes
fewer instructions to execute a given workload and simultaneously you
have not screwed up the pipeline frequency so the ISA gains drop all the way to the bottom line.

John Savard