Re: Oops (Concertina II Going Around in Circles)

On Fri, 10 May 2024 18:34:09 -0600, John Savard
<quadibloc@servername.invalid> wrote:

On Fri, 10 May 2024 21:06:58 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:

With MEM-OPs are you not already CISC ??

>
I should have been clearer, but to tell the truth would have taken
many words.
>
What I meant was that while Concertina II indeed is hardly RISC, it
still contains a near-RISC instruction set in the basic 32-bit
operations. Unlike typical RISC instruction sets, it has base plus
index addressing, though.
>
Then mem-ops are added in the first supplementary instruction set,
yes. Concertina II is intended to be "architecture-agnostic", being at
once sort of like RISC, but also VLIW and CISC.
>
What Concertina III would give up, to no longer be RISC at all, would
be register banks of 32 registers. Changing that to 8 registers
shortens certain fields, letting me switch to native variable-length
instructions without the need for any block header mechanism.

The headers divide the architecture into its code types.

If no headers are used, the available instruction set is basically a
RISC instruction set... with more than the usual amount of
instructions, and with base + index addressing.

Using type I headers adds immediates.

If one is producing VLIW-style code, one will use the type II header.

If one uses the type III header, then one has a CISC instruction set,
with different lengths of instructions, memory to register operate
instructions, string instructions, and so on. This is true of the type
VI and VIII headers.

The type VII header combines VLIW with CISC; then one will liikely
also use the encapsulation mechanism to place long instructions within
blocks with a type II header to use all the VLIW features.

The type III header extends the instruction set, without otherwise
departing from a RISC-style instruction set.

So a compiler, at least on any one code generation setting, would use
only a subset of the available headers - although one that can
generate both CISC and VLIW code as requested is certainly a
possibility.

John Savard