Sujet : Re: Oops (Concertina II Going Around in Circles)
De : quadibloc (at) *nospam* servername.invalid (John Savard)
Groupes : comp.archDate : 12. May 2024, 10:57:02
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <de414j9t5vo05idmkga2097ui3te2obj2q@4ax.com>
References : 1 2
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On Thu, 9 May 2024 20:28 +0100 (BST),
jgd@cix.co.uk (John Dallman)
wrote:
In article <fajp3j12esafhpn3e27ntfq5f538jmb3q7@4ax.com>,
quadibloc@servername.invalid (John Savard) wrote:
>
Of course, this sort of thing may leave you gasping in shock and
horror. But look at the bright side. While 128 is a somewhat large
number, it isn't astronomical; I haven't provided for an opcode
space so large that there isn't enough matter in the whole Universe to
print a programmer's manual for the architecture.
>
Now, _that_ would be genuinely impracitcal!
Of course, as these many additional sets of instructions get fleshed
out, were the ISA to be implemented
>
I think you've just added another couple of orders of magnitude to the
odds against that happening.
I've decided to claw some of those orders of magnitude back, even if
it hardly matters (zero divided by 100 is still zero).
Now I've changed the applicable header format to provide only _eight_
additional alternate instruction sets, instead of almost 128 of them,
using the available bits instead for something much more important -
allowing the explicit indication of parallelism to be easily combined
with the use of all of the first four instruction sets, as well as one
of the eight new ones.
John Savard