Re: Article on the 8088 bus cycle

BGB wrote:

Seems like probably in a similar area as QSPI RAM.

Quick skim, looks like QSPI RAM access looks something like:
   Pull CS low;
   Send command byte;
   Send address bytes (4);
   Send/receive data bytes;
   CS goes high when transfer is done;
     CS going high apparently puts the chip back in its idle state.

If you do a 16-byte burst, this would be ~ 1.4 cycles (DDR) per data byte, or 2.8 cycles if driving it from a faster SDR clock. A datasheet for a random QSPI RAM chip I found suggests it has a maximum operating frequency of around 54 MHz (so, a little lower than the DDR chips), and a lot are apparently "pseudo static" (they are DRAM internally, but also perform their own RAM refresh, appearing as SRAM from the POV of the external bus interface).

You are forgetting that DRAM RAS occurs after the first 2 address bytes
are latched, and that CAS occurs after the second 2 address bits are latched {and that you are in a deRAS deCAS state already.}
QSPI at 54 Mhz is just under 20ns per DRAM address/command event not that
much different than current DDRs
But what current DDRs can do is to partially overlap address/command with
data transfer--I would suspect QSPI could do this too.