Re: Article on the 8088 bus cycle

On Wed, 15 May 2024 21:41:32 +0000
mitchalsup@aol.com (MitchAlsup1) wrote:

BGB wrote:
 

Seems like probably in a similar area as QSPI RAM. 

 

Quick skim, looks like QSPI RAM access looks something like:
   Pull CS low;
   Send command byte;
   Send address bytes (4);
   Send/receive data bytes;
   CS goes high when transfer is done;
     CS going high apparently puts the chip back in its idle state.
 

 
 

If you do a 16-byte burst, this would be ~ 1.4 cycles (DDR) per
data byte, or 2.8 cycles if driving it from a faster SDR clock. A
datasheet for a random QSPI RAM chip I found suggests it has a
maximum operating frequency of around 54 MHz (so, a little lower
than the DDR chips), and a lot are apparently "pseudo static" (they
are DRAM internally, but also perform their own RAM refresh,
appearing as SRAM from the POV of the external bus interface). 

 
You are forgetting that DRAM RAS occurs after the first 2 address
bytes are latched, and that CAS occurs after the second 2 address
bits are latched {and that you are in a deRAS deCAS state already.}
 

We are talking about 1978 here. Back then, it was 7-bit raw addres
and 7-bit column addresss. I don't know how they applied address bits
above A13. Later on there were chip select and/or output enable signals,
but circa-1978 16-bit DRAM had neither of those. So, it seems, if one
wanted to put more than 16 KB on 8-bit bus, one had to generated
multiple sets of RAS# and CAS# signals.

Since then # of rows, first per DRAM chip and later per bank, grew
tremendously, but number of columns only grew by factor of 8 and
remains the same for more than 20 years.

QSPI at 54 Mhz is just under 20ns per DRAM address/command event not
that much different than current DDRs
 
But what current DDRs can do is to partially overlap address/command
with data transfer--I would suspect QSPI could do this too.

Partially?
With typical CL=14==28T, and with burst that just recently was
increased to 16T and before that stayed at 8T for more than decade, I'd
say that it's full overlap ++.