Re: Article on the 8088 bus cycle

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Sujet : Re: Article on the 8088 bus cycle
De : cr88192 (at) *nospam* gmail.com (BGB)
Groupes : comp.arch
Date : 16. May 2024, 01:48:44
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <v23hl3$15h5l$1@dont-email.me>
References : 1 2 3 4
User-Agent : Mozilla Thunderbird
On 5/15/2024 5:35 PM, David Schultz wrote:
On 5/15/24 3:30 PM, BGB wrote:
In my case, I hadn't found much information about accessing SDcards in anything other than SPI mode, but I guess if it turns out it is basically just QSPI and the same byte-oriented protocol as before, that would be useful to know.
>
The SD card specification covers both in detail.
 
When looking around before, I generally only found people talking about the SPI interfaces. Granted, I didn't have the official specifications (which seemed to be paywalled and not generally available otherwise). I mostly implemented stuff based on information I found on various websites.
Though, looking around some more, apparently the 4-bit interface is basically the same protocol (at the byte level) as the 1-bit SPI protocol, but differs mostly in that it is 4-bit SDR (apparently the DDR variants are specific to UHS-I / UHS-II, and the "Full Speed" variant that is SDR).
Apparently, it is also functionally equivalent to QSPI is most other regards (well, apart from QSPI RAM/Flash and SDcards having different communication protocols).

But the 4 bit wide SD access will depend a lot on what hardware support you have. I used an ARM (in a Teensy 3.2) to do the job. Mostly quite similar to SPI access.
 
I am mostly using FPGA's here, so in theory shouldn't be too much effort to add QSPI support.
Bigger challenge is figuring out how to best modify the design of the SPI MMIO interface to be able to make use of the higher data transfer speeds.
Though most immediate solution would probably just be to add some more MMIO registers to increase the data-transfer size; though this quickly turns into diminishing returns.
Another possibility being to widen the MMIO Bus interface to 128 bits.
Mostly, the limiting factor is that it takes roughly 24 clock cycles for every access to the MMIO bus in my case.
Though, looks like increasing the transfer size to 32 bytes (via adding more MMIO registers and a few more control bits) would increase the bottleneck to around 14MB/s, which looks like mostly enough to make effective use of SDcard 4-bit / Full Speed mode...

 

Date Sujet#  Auteur
13 May 24 * Article on the 8088 bus cycle13Thomas Koenig
13 May 24 +- Re: Article on the 8088 bus cycle1MitchAlsup1
15 May 24 `* Re: Article on the 8088 bus cycle11Terje Mathisen
15 May 24  `* Re: Article on the 8088 bus cycle10BGB
15 May 24   +* Re: Article on the 8088 bus cycle3MitchAlsup1
16 May 24   i+- Re: Article on the 8088 bus cycle1Michael S
18 May 24   i`- Re: Article on the 8088 bus cycle1BGB-Alt
16 May 24   `* Re: Article on the 8088 bus cycle6David Schultz
16 May 24    `* Re: Article on the 8088 bus cycle5BGB
16 May 24     `* Re: Article on the 8088 bus cycle4David Schultz
16 May 24      `* Re: Article on the 8088 bus cycle3BGB-Alt
17 May 24       `* Re: Article on the 8088 bus cycle2David Schultz
17 May 24        `- Re: Article on the 8088 bus cycle1BGB

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